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P re liminary Spe c ification, Versio n 1.1, 2 002-11-28
TDA5255 E1 ASK/FSK 434MHz Wireless Transceiver
Wireless Components
Never
stop
thinking.
Edition 2002-11-28 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 11/29/02.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
P re liminary Spe c ification, Versio n 1.1, 2 002-11-28
TDA5255 E1 ASK/FSK 434MHz Wireless Transceiver
Wireless Components
Never
stop
thinking.
Preliminary Specification Confidential Revision History: 2002-11-28 Previous Version: Page 12 13 14,15 31 85 87 1.0, 2002-10-30 Subjects (major changes since last revision)
TDA5255 E1
Wrong pin names and description at pin 7 and 8 corrected Additional note at pin 15 Correction of pin names Serial resistor in VDD supply line Serial resistor in VDD supply line Serial resistor in VDD supply line
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Confidential
ASK/FSK 434MHz Wireless Transceiver TDA5255 E1
Version 1.1
Product Info
General Description The IC is a low power consumption single chip FSK/ASK Transceiver for half duplex low datarate communication in the 433-435MHz band. The IC offers a very high level of integration and needs only a few external components. It contains a highly efficient power amplifier, a low noise amplifier (LNA) with AGC, a double balanced mixer, a complex direct conversion stage, I/ Q limiters with RSSI generation, an FSK demodulator, a fully integrated VCO and PLL synthesizer, a tuneable crystal oscillator, an onboard data filter, a data comparator (slicer), positive and negative peak detectors, a data rate detection circuit and a 2/3-wire bus interface. Additionally there is a power down feature to save battery power.
Features
- Low supply current (Is = 9mA typ. receive, Is = 13mA typ. transmit mode) - Supply voltage range 2.1 - 5.5V - Power down mode with very low supply current consumption - FSK and ASK modulation and demodulation capability - Fully integrated VCO and PLL synthesizer and loop filter on-chip with on chip crystal oscillator tuning - I2C/3-wire Controller Interface - On-chip low pass channel select filter and data filter with tuneable bandwidth - Data slicer with self-adjusting threshold and 2 peak detectors - FSK sensitivity <-109dBm, ASK sensitivity < -109dBm - Transmit power up to +13dBm - Datarates up to 100kBit/s Manchester Encoded - Self-polling logic with ultra fast data rate detection
Application
- Low Bitrate Communication Systems - Keyless Entry Systems - Remote Control Systems - Alarm Systems - Telemetry Systems - Electronic Metering - Home Automation Systems
Type TDA5255 E1 Preliminary Specification
Ordering Code
Package P-TSSOP-38-1
5
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TDA5255 E1 Version 1.1
Confidential
Table of Contents
page
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 1.2 1.3 1.4
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 8 9 9
10
2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.4.13 2.4.14 2.4.15 2.4.16 2.4.17 2.4.18 2.4.19 2.4.20
3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Amplifier (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Downconverter 1st Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Downconverter 2nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/Q Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/Q Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bandgap Reference Circuitry and Powerdown . . . . . . . . . . . . . Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface and Register Definition . . . . . . . . . . . . . . . . . . . . Wakeup Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 11 17 18 18 18 18 18 19 19 20 20 21 21 21 21 22 22 23 30 31 32 34 35
37
3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2
LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch in RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch in TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
37 37 37 40 42 48
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Preliminary Specification
TDA5255 E1 Version 1.1
Confidential
Table of Contents
page
3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.3 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.7 3.7.1 3.7.2 3.8 3.9 3.10 3.10.1 3.10.2 3.10.3 3.11
4
Synthesizer Frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive ASK/FSK Frequency Assignment . . . . . . . . . Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculation of the external capacitors . . . . . . . . . . . . . . . . . . . . FSK-switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Finetuning and FSK modulation relevant registers . . . . . . . . . . Chip and System Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . IQ-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiter and RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer - Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detector - Analog output signal . . . . . . . . . . . . . . . . . . . . Peak Detector - Power Down Mode . . . . . . . . . . . . . . . . . . . . . Data Valid Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Window for Data Rate Detection . . . . . . . . . . . . . . . RSSI threshold voltage - RF input power . . . . . . . . . . . . . . . . . Calculation of ON_TIME and OFF_TIME . . . . . . . . . . . . . . . . . . . Example for Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensitivity Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BER performance depending on Supply Voltage . . . . . . . . . . . Datarates and Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51 51 53 55 55 56 57 58 59 60 62 62 63 65 65 66 68 69 69 70 71 71 73 74 75
77
4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.3 4.4
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77 77 77 78 81 84 85 86
Preliminary Specification
7
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Confidential Product Description
1
1.1
Product Description
Overview
The IC is a low power consumption single chip FSK/ASK Transceiver for the frequency band 433435 MHz. The IC combines a very high level of integration and minimum external part count. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesizer, a crystal oscillator with FSK modulator, a limiter with RSSI generator, an FSK demodulator, a data filter, a data comparator (slicer), a positive and a negative data peak detector, a highly efficient power amplifier and a complex digital timing and control unit with I2C/3-wire microcontroller interface. Additionally there is a power down feature to save battery power. The transmit section uses direct ASK modulation by switching the power amplifier, and crystal oscillator detuning for FSK modulation. The necessary detuning load capacitors are external. The capacitors for fine tuning are integrated. The receive section is using a novel single-conversion/ direct-conversion scheme that is combining the advantages of both receive topologies. The IF is contained on the chip, no RF channel filters are necessary as the channel filter is also on the chip. The self-polling logic can be used to let the device operate autonomously as a master for a decoding microcontroller.
1.2
Features
- Low supply current (Is = 9 mA typ. receive, Is = 13mA typ. transmit mode, both at 3 V supply voltage, 25C) - Supply voltage range 2.1 V to 5.5 V - Operating temperature range -40C to +85C - Power down mode with very low supply current consumption - FSK and ASK modulation and demodulation capability without external circuitry changes, FM demodulation capability - Fully integrated VCO and PLL synthesizer and loop filter on-chip with on-chip crystal oscillator tuning, therefore no additional external components necessary - Differential receive signal path completely on-chip, therefore no external filters are necessary - On-chip low pass channel select and data filter with tuneable bandwith - Data slicer with self-adjusting threshold and 2 peak detectors - Self-polling logic with adjustable duty cycle and ultrafast data rate detection and timer mode providing periodical interrupt - FSK and ASK sensitivity < -109 dBm - Adjustable LNA gain - Digital RSSI and Battery Voltage Readout - Provides Clock Out Pin for external microcontroller - Transmit power up to +13 dBm in 50W load at 5V supply voltage - Maximum datarate up to 100 kBaud Manchester Encoded - I2C/3-wire microcontroller interface, working at max. 400kbit/s - meets the ETSI EN300 220 regulation and CEPT ERC 7003 recommendation
Preliminary Specification
8
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Confidential Product Description
1.3
- - - - - - -
Application
Low Bitrate Communication Systems Keyless Entry Systems Remote Control Systems Alarm Systems Telemetry Systems Electronic Metering Home Automation Systems
1.4
Package Outlines
P-TSSOP-38-1.EPS
Figure 1-1
P-TSSOP-38-1 package outlines
Preliminary Specification
9
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Confidential Functional Description
2
2.1
Functional Description
Pin Configuration
VCC BUSMODE LF ____ ASKFSK __ RxTx LNI LNIx GND1 GNDPA PA VCC1 PDN PDP SLC VDD BUSDATA BUSCLK VSS XOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
CI1 CI1x CQ1 CQ1x CI2 CI2x CQ2 CQ2x GND RSSI DATA ___ PWDDD CLKDIV ______ RESET ___ EN XGND XSWA XIN XSWF
5255E1_pin_conf.wmf
Figure 2-1
Pin Configuration
Preliminary Specification
10
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Confidential Functional Description
2.2
Pin Definitions and Functions
Table 2-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic 1 VCC
Function Analog supply (antiparallel diodes between VCC, VCC1, VDD)
11
1
15
2
BUSMODE
Bus mode selection (IC/3 wire bus mode selection)
350 2
3
LF
Loop filter and VCO control voltage
200 3
4
ASKFSK
ASK/FSK- mode switch input
350 4
Preliminary Specification
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5 RXTX
Functional Description
RX/TX-mode switch input/output
350 5 TX
6
LNI
RF input to differential Low Noise Amplifier (LNA))
5k 6 1.1V 5k 7
180 PWDN
180 PWDN
7 8
LNIX GND1
see Pin 6
Complementary RF input to differential LNA Ground return for LNA and Power Amplifier (PA) dirver stage
30
8
18
9
9 10
GNDPA PA
10
see Pin 8
Ground return for PA output stage PA output stage
10 W
9 GndPA
11
VCC1
see Pin 1
Supply for LNA and PA
Preliminary Specification
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12 PDN
PWDN 350 12 50k 50k
Functional Description
Output of the negative peak detector
3k
13
PDP
50k 50k
Output of the positive peakdetector
350 13 PWDN
3k
14
SLC
1.2uA 50k 50k
Slicer level for the data slicer
350 14
50k
50k
1.2uA
50k
50k
15
VDD
see Pin 1
16
BUSDATA
Digital supply; A 10W serial resistor in the VDD supply line is strongly recommended; see also Section 4.4 Bus data in/output
15k 350 16
17
BUSCLK
Bus clock input
350 17
Preliminary Specification
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18 19 VSS XOUT see Pin 8
Functional Description
Ground for digital section Crystal oscillator output, can also be used as external reference frequency input.
Vcc
4k Vcc-860mV 150mA 19
20
XSWF
21 125fF ..... 4pF
FSK modulation switch
20 250fF ..... 8pF 23
21 22
XIN XSWA
see Pin 20 ASK modulation/FSK center frequency switch
22
20
23
23 24
XGND EN
see Pin 22
Crystal oscillator ground return 3-wire bus enable input
350 24
Preliminary Specification
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25 RESET
Functional Description
Reset of the entire system (to default values), active low
110k 350 25 10p
26
CLKDIV
Clock output
350 26
27
PWDDD
Power Down input (active high), data detect output (active low)
30k 350 27
28
DATA
TX Data input, RX data output (RX powerdown: pin 28 @ GND)
350 28
29
RSSI
RSSI output
350 29 37k 16p
S&H
Preliminary Specification
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30 31 GND CQ2x see Pin 8
Functional Description
Analog ground Pin for external Capacitor Q-channel, stage 2
Stage1:Vcc-630mV Stage2: Vcc-560mV 31
32 33 34 35 36 37 38
CQ2 CI2x CI2 CQ1x CQ1 CI1x CI1
II II II II II II II
Q-channel, stage 2 I-channel, stage 2 I-channel, stage 2 Q-channel, stage 1 Q-channel, stage 1 I-channel, stage 1 I-channel, stage 1
Preliminary Specification
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2.3
14 16 28 FSK 26 27 5 4 Data FILTER + SLICER 100k ASK/FSK 13 PDP WAKEUP LOGIC ASK QUADRI CORRELATOR CONTROLLER INTERFACE 17 24 2
Preliminary Specification
BUSCLK BUSDATA BUSMODE __ EN
SLC
Figure 2-2
31 32 33 34 35 36 37 38 CQ1x CQ1 CI1x CI1 CQ2x CQ2 CI2x CI2
Data (RX/TX) CLKDIV PWDDD RXTX ASKFSK MIXER fIF= 144.7MHz Channel Filter
Confidential
VCC1
VCC
VDD
11
1
15
(digital)
(analog)
(LNA/PA)
ANT
fRF= 434.15MHz
LIMITER
LNI LP FILTER
6
I Q
MIXER Channel Filter
single ended to differential conv.
LNA
MIXER
Functional Block Diagram
Main Block Diagram
LIMITER
100k f = 144.7MHz 100k +Peak Det
7
LNIx
h ig h/lo w G a in
17
RSSI
-Peak Det
12
PDN
0 90 :4
ASK DATA TX/RX ASK/FSK TX/RX :6/8 6-bit SAR-ADC
VCC
25 Bandgap Reference
RESET
ANT
29
RSSI
PA :2 VCO LOOP FILTER
10
CLK CRYSTAL Osc, FSKMod, Finetuning FSK DATA (LNA/PA) (analog) 19 XOUT 21 XIN 20 XSWF 22 XSWA 23 XGND Gnd1 fQ= 18.0896MHz Gnd Vss 8 30 (digital) 18
PA
PHASE DET. Charge P.
fTX= 434.15MHz 3
9
fRX= 578.85MHz
GndPA LF
Functional Description
TDA5255E1_blockdiagram_aktuell.wmf
TDA5255 E1 Version 1.1
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TDA5255 E1 Version 1.1
Confidential Functional Description
2.4 2.4.1
Functional Block Description Power Amplifier (PA)
The power amplifier is operating in C-mode. It can be used in either high or low power mode. In high-power mode the transmit power is approximately +13dBm into 50 Ohm at 5V and +6dBm at 2.1V supply voltage. In low power mode the transmit power is approximately +10dBm at 5V and 32dBm at 2.1V supply voltage using the same matching network. The transmit power is controlled by the D0-bit of the CONFIG register (subaddress 00H) as shown in the following Table 2-2. The default output power mode is high power mode. Table 2-2 Bit D0 Sub Address 00H: CONFIG Function Description PA_PWR 0= low TX Power, 1= high TX Power
Default 1
In case of ASK modulation the power amplifier is turned fully on and off by the transmit baseband data, i.e. 100% On-Off-Keying.
2.4.2
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB and symmetrical inputs. It is possible to reduce the gain to 0 dB via logic. Table 2-3 Bit D4 Sub Address 00H: CONFIG Function Description LNA_GAIN 0= low Gain, 1= high Gain
Default 1
2.4.3
Downconverter 1st Mixer
The Double Balanced 1st Mixer converts the input frequency (RF) in the range of 434-435 MHz to down to the intermediate frequency (IF) at approximately 144MHz. The local oscillator frequency is generated by the PLL synthesizer that is fully implemented on-chip as described in Section 2.4.5. This local oscillator operates at approximately 578MHz in receive mode providing the above mentioned IF frequency of 144MHz. The mixer is followed by a low pass filter with a corner frequency of approximately 175MHz in order to prevent RF and LO signals from appearing in the 144MHz IF signal.
2.4.4
Downconverter 2nd I/Q Mixers
The Low pass filter is followed by 2 mixers (inphase I and quadrature Q) that convert the 144MHz IF signal down to zero-IF. These two mixers are driven by a signal that is generated by dividing the local oscillator signal by 4, thus equalling the IF frequency.
Preliminary Specification
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2.4.5
PLL Synthesizer
The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a divider by 4, an asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCOs are including spiral inductors and varactor diodes. The center frequency of the transmit VCO is 868MHz, the center frequency of the receive VCO is 1156MHz. Generally in receive mode the relationship between local oscillator frequency fosc, the receive RF frequency fRF and the IF frequency fIF and thus the frequency that is applied to the I/Q Mixers is given in the following formula:
f osc = 4/3 f RF = 4 f IF 2
[2 - 1]
The VCO signal is applied to a divider by 2 and afterwards by 4 which is producing approximately 144MHz signals in quadrature. The overall division ratio of the divider chain following the divider by 2 and 4 is 6 in transmit mode and 8 in receive mode as the nominal crystal oscillator frequency is 18.083MHz. The division ratio is controlled by the RxTx pin (pin 5) and the D10 bit in the CONFIG register.
2.4.6
I/Q Filters
The I/Q IF to zero-IF mixers are followed by baseband 6th order low pass filters that are used for RF-channel filtering.
OP
INTERNAL BUS
iq_filter.wmf
Figure 2-3
One I/Q Filter stage
The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted between 50 and 350kHz in 50kHz steps via the bits D1 to D3 of the LPF register (subaddress 03H).
Preliminary Specification
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2.4.7
I/Q Limiters
The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz. Receive Signal Strength Indicator (RSSI) generators are included in both limiters which produce DC voltages that are directly proportional to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI signal.
2.4.8
FSK Demodulator
The output differential signals of the I/Q limiters are fed to a quadrature correlator circuit that is used to demodulate frequency shift keyed (FSK) signals. The demodulator gain is 2.4mV/kHz, the maximum frequency deviation is 300kHz as shown in Figure 2-4 below. The demodulated signal is applied to the ASK/FSK mode switch which is connected to the input of the data filter. The switch can be controlled by the ASKFSK pin (pin 4) and via the D11 bit in the CONFIG register. The modulation index m must be larger than 2 for correct demodulation of the signal.
1,6 1,5 1,4 1,3 1,2 U /V 1,1 1 0,9 0,8 0,7 0,6 0,5 -350 -300 -250 -200 -150 -100 -50 0 f /kHz
Qaudricorrelator.wmf
50
100 150 200 250 300 350
Figure 2-4
Quadricorrelator Demodulation Characteristic
Preliminary Specification
20
2002-11-28
TDA5255 E1 Version 1.1
Confidential Functional Description
2.4.9
Data Filter
The 2-pole data filter has a Sallen-Key architecture and is implemented fully on-chip. The bandwidth can be adjusted between approximately 5kHz and 102kHz via the bits D4 to D7 of the LPF register as shown in Table 3-10.
ASK / FSK
OTA
INTERNAL BUS
data_filter.wmf
Figure 2-5
Data Filter architecture
2.4.10
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100kHz. The self-adjusting threshold is generated by a RC-network (LPF) or by use of one or both peak detectors depending on the baseband coding scheme as described in Section 3.6. This can be controlled by the D15 bit of the CONFIG register as shown in the following table. Table 2-4 Bit D15 Sub Address 00H: CONFIG Function Description SLICER 0= Lowpass Filter, 1= Peak Detector
Default 0
2.4.11
Peak Detectors
Two separate Peak Detectors are available. They are generating DC voltages in a fast-attack and slow-release manner that are proportional to the positive and negative peak voltages appearing in the data signal. These voltages may be used to generate a threshold voltage for non-Manchester encoded signals, for example. The time-constant of the fast-attack/slow-release action is determined by the RC network with external capacitor.
2.4.12
Crystal Oscillator
The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal operating in serial resonance. The nominal operating frequency of 18.083MHz and the frequencies for FSK modulation can be adjusted via 3 external capacitors. Via microcontroller and bus interface the chip-internal capacitors can be used for finetuning of the nominal and the FSK modulation frequencies. This finetuning of the crystal oscillator allows to eliminate frequency errors due to crystal or component tolerances.
Preliminary Specification
21
2002-11-28
TDA5255 E1 Version 1.1
Confidential Functional Description
2.4.13
Bandgap Reference Circuitry and Powerdown
A Bandgap Reference Circuit provides a temperature stable 1.2V reference voltage for the device. A power down mode is available to switch off all subcircuits that are controlled by the bidirectional Powerdown&DataDetect PwdDD pin (pin 27) as shown in the following table. Power down mode can either be activated by pin 27 or bit D14 in Register 00. In power down mode also pin 28 (DATA) is affected (see Section 2.4.17). Table 2-5 PwdDD Pin Operating States PwdDD VDD Ground/VSS
Operating State Powerdown Mode Device On
2.4.14
Timing and Data Control Unit
The timing and data control unit contains a wake-up logic unit, an I2C/3-wire microcontroller interface, a "data valid" detection unit and a set of configuration registers as shown in the subsequent figure.
BusMode BusData BusCLK
I2C / 3Wire INTERFACE
REGISTERS
EN
18 MHz XTAL-Osz.
INTERNAL BUS
DATA VALID DETECTOR
RSSI
WAKEUP LOGIC
6 B it ADC
A M P LITU D E thres hold T H 3 FREQUENCY window TH1RF - BLOCK
32kHz RC-Osz.
RX DATA
FSK DATA ASK DATA BLOCK ENABLE ASK / FSK RX / TX
ENABLE
DATA VALID
CONTROL LOGIC
CLKDiv PwdDD Data AskFsk
POWER ON SEQUENCER
RxTx Reset
logic.wmf
Figure 2-6
Timing and Data Control Unit 22 2002-11-28
Preliminary Specification
TDA5255 E1 Version 1.1
Confidential Functional Description
The I2C / 3-wire Bus Interface gives an external microcontroller full control over important system parameters at any time. It is possible to set the device in three different modes: Slave Mode, Self Polling Mode and Timer Mode. This is done by a state machine which is implemented in the WAKEUP LOGIC unit. A detailed description is given in Section 2.4.16. The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold comparator. The window counter uses the incoming data signal from the data slicer as the gating signal and the crystal oscillator frequency as the timebase to determine the actual datarate. The result is compared with the expected datarate. The threshold comparator compares the actual RSSI level with the expected RSSI level. If both conditions are true the PwdDD pin is set to LOW in self polling mode as you can see in Section 2.4.16. This signal can be used as an interrupt for an external P. Because the PwdDD pin is bidirectional and open drain driven by an internal pull-up resistor it is possible to apply an external LOW thus enabling the device.
2.4.15
Bus Interface and Register Definition
The TDA5255 supports the I2C bus protocol (2 wire) and a 3-wire bus protocol. Operation is selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData, BusCLK, EN, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional where the output is open drain driven by an internal 15kW pull up resistor. Table 2-6 Bus Interface Format Function BusMode Low I2C Mode 3-wire Mode High
EN High= inactive, Low= active
BusCLK Clock input
BusData Data in/out
BusData 16 FRONTEND BusCLK 17 EN 24 BusMode 2 11100000
CHIP ADDRESS
I2C / 3-wire INTERFACE
INTERNAL BUS
i2c_3w_bus.wmf
Figure 2-7
Bus Interface
Note: The Interface is able to access the internal registers at any time, even in POWER DOWN mode. There is no internal clock necessary for Interface operation. Preliminary Specification 23 2002-11-28
TDA5255 E1 Version 1.1
Confidential I2C Bus Mode
In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW. Data Transition: Data transition on the pin BusData can only occur when BusCLK is LOW. BusData transitions while BusCLK is HIGH will be interpreted as start or stop condition. Start Condition (STA): A start condition is defined by a HIGH to LOW transition of the BusData line while BusCLK is HIGH. This start condition must precede any command and initiate a data transfer onto the bus. Stop Condition (STO): A stop condition is defined by a LOW to HIGH transition of the BusData line while BusCLK is HIGH. This condition terminates the communication between the devices and forces the bus interface into the initial state. Acknowledge (ACK): Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will set the SDA line to LOW level to indicate it has received the 8 bits of data correctly. Data Transfer Write Mode: To start the communication, the bus master must initiate a start condition (STA), followed by the 8bit chip address. The chip address for the TDA5255 is fixed as 1110000" (MSB at first). The last bit (LSB=A0) of the chip address byte defines the type of operation to be performed: A0=0, a write operation is selected and A0=1 a read operation is selected. After this comparison the TDA5255 will generate an ACK and awaits the desired sub address byte (00H...0FH) and data bytes. At the end of the data transition the master has to generate the stop condition (STO). Data Transfer Read Mode: To start the communication in the read mode, the bus master must initiate a start condition (STA), followed by the 8 bit chip address (write: A0=0), followed by the sub address to read (80H, 81H), followed by the chip address (read: A0=1). After that procedure the data of the selected register (80H, 81H) is read out. During this time the data line has to be kept in HIGH state and the chip sends out the data. At the end of data transition the master has to generate the stop condition (STO).
Functional Description
Preliminary Specification
24
2002-11-28
TDA5255 E1 Version 1.1
Confidential Bus Data Format in I2C Mode
Table 2-7 MSB 1 1 Table 2-8
MSB STA 1 1 1
Functional Description
Chip address Organization 1 1 1 1 0 0 0 0 0 0 0 0 LSB 0 1 Function Chip Address Write Chip Address Read
I2C Bus Write Mode 8 Bit
CHIP ADDRESS (WRITE) 0 0 0 0 LSB 0 ACK MSB S7 SUB ADDRESS (WRITE) 00H...08H, 0DH, 0EH, 0FH S6 S5 S4 S3 S2 S1 LSB MSB DATA IN LSB S0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STO
Table 2-9
MSB STA 1 1 1
I2C Bus Write Mode 16 Bit
MSB ACK S7 S6 SUB ADDRESS (WRITE) 00H...08H, 0DH, 0EH, 0FH S5 S4 S3 S2 S1 LSB S0 MSB DATA IN LSB D0 ACK STO 0 0 0 0 0 ACK D15 ... D8 ACK D7 D6 ...
CHIP ADDRESS (WRITE) LSB
Table 2-10
STA 1 1 1 0
I2C Bus Read Mode
MSB ACK S7 S6 SUB ADDRESS (READ) 80H, 81H S5 S4 S3 S2 S1 LSB S0 ACK STA MSB 1 CHIP ADDRESS (READ) 1 1 0 0 0 0 LSB 1 ACK 0 0 0 0
MSB CHIP ADDRESS (WRITE) LSB
Table 2-10
MSB R7
I2C Bus Read Mode (continued)
DATA OUT FROM SUB ADDRESS R6 R5 R4 R3 R2 R1 LSB R0 ACK* STO
* mandatory HIGH
3-wire Bus Mode
In this mode pin 2 (BusMode)= HIGH and Pin 16 (BusData) is in the data input/output pin. Pin 24 (EN) is used to activate the bus interface to allow the transfer of data to / from the device. When pin 24 (EN) is inactive (HIGH), data transfer is inhibited. Data Transition: Data transition on pin 16 (BusData) can only occur if the clock BusCLK is LOW. To perform a data transfer the interface has to be enabled. This is done by setting the EN line to LOW. A serial transfer is done via BusData, BusCLK and EN. The bit stream needs no chip address. Data Transfer Write Mode: To start the communication the EN line has to be set to LOW. The desired sub address byte and data bytes have to follow. The subaddress (00H...0FH) determines which of the data bytes are transmitted. At the end of data transition the EN must be HIGH. Data transfer Read Mode: To start the communication in the read mode, the EN line has to be set to LOW followed by the sub address to read (80H, 81H). Afterwards the device is ready to read out data. At the end of data transition EN must be HIGH.
Preliminary Specification
25
2002-11-28
TDA5255 E1 Version 1.1
Confidential Bus Data Format 3-wire Bus Mode Functional Description
Table 2-11 3-wire Bus Write Mode MSB SUB ADDRESS (WRITE) 00H...08H, 0DH, 0EH,0FH S7 S6 S5 S4 S3 S2 S1 Table 2-12 3-wire Bus Read Mode MSB SUB ADDRESS (READ) 80H, 81H S7 S6 S5 S4 S3 S2 S1
LSB MSB S0 DX ...
DATA IN X...0 (X=7 or 15) D5 D4 D3 D2 D1
LSB D0
LSB MSB S0 R7 R6
DATA OUT FROM SUB ADDRESS R5 R4 R3 R2
LSB R1 R0
Register Definition
Sub Addresses Overview
ADC
RSSI [8 Bit]
FILTER I2C - SPI INTERFACE
LPF [8 Bit]
CONTROL
CONFIG [16 Bit] STATUS [8 Bit] CLK_DIV [8 Bit] BLOCK_PD [16Bit]
WAKEUP
ON_TIME [16 Bit] OFF_TIME [16 Bit] COUNT_TH1 [16Bit] COUNT_TH2 [16Bit] RSSI_TH3 [8 Bit]
XTAL
XTAL_TUNE [16Bit] FSK [16Bit] XTAL_CONFIG [8 Bit]
register_overview.wmf
Figure 2-8
Sub Addresses Overview
Preliminary Specification
26
2002-11-28
TDA5255 E1 Version 1.1
Confidential Subaddress Organization
Table 2-13
MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Functional Description
Sub Addresses of Data Registers Write
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 0 1 0 1 HEX 00h 01h 02h 03h 04h 05h 06h 07h 08h 0Dh 0Eh 0Fh Function CONFIG FSK XTAL_TUNING LPF ON_TIME OFF_TIME COUNT_TH1 COUNT_TH2 RSSI_TH3 CLK_DIV XTAL_CONFIG BLOCK_PD Description General definition of status bits Values for FSK-shift Nominal frequency I/Q and data filter cutoff frequencies ON time of wakeup counter OFF time of wakeup counter Lower threshold of window counter Higher threshold of window counter Threshold for RSSI signal Configuration and Ratio of clock divider XTAL configuration Building Blocks Power Down Bit Length 16 16 16 8 16 16 16 16 8 8 8 16
Table 2-14
MSB 1 1 0 0 0 0 0 0
Sub Addresses of Data Registers Read
LSB HEX 0 0 0 0 0 0 0 1 80h 81h Function STATUS ADC Description Results of comparison: ADC & WINDOW ADC data out Bit Length 8 8
Data Byte Specification
Table 2-15
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Sub Address 00H: CONFIG
Function SLICER ALL_PD TESTMODE CONTROL ASK_NFSK RX_NTX CLK_EN RX_DATA_INV D_OUT ADC_MODE F_COUNT_MODE LNA_GAIN EN_RX MODE_2 MODE_1 PA_PWR Description 0= Lowpass, 1= Peak Detector 0= normal operation, 1= all Power down 0= normal operation, 1=Testmode 0= RX/TX and ASK/FSK external controlled, 1= Register controlled 0= FSK, 1=ASK 0= TX, 1=RX 0= CLK off during power down, 1= always CLK on, ever in PD 0= no Data inversion, 1= Data inversion 0= Data out if valid, 1= always Data out 0= one shot, 1= continuous 0= one shot, 1= continuous 0= low gain, 1= high gain 0= disable receiver, 1= enable receiver (in self polling and timer mode) * 0= slave mode, 1= timer mode 0= slave or timer mode, 1= self polling mode 0= low TX Power, 1= high TX Power Default 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 1
Note D3: Function is only active in selfpolling and timer mode. When D3 is set to LOW the RX path is not enabled if PwdDD pin is set to LOW. A delayed setting of D3 results in a delayed power ON of the RX building blocks.
Preliminary Specification
27
2002-11-28
TDA5255 E1 Version 1.1
Confidential Functional Description
Table 2-16 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FSK-5 FSK-4 FSK-3 FSK-2 FSK-1 FSK-0 FSK+5 FSK+4 FSK+3 FSK+2 FSK+1 FSK+0 Function
Sub Address 01H: FSK Value Description not used not used 8pF 4pF 2pF 1pF 500fF 250fF not used not used 4pF 2pF 1pF 500fF 250fF 125fF Setting for negative frequency shift: -FSK Setting for positive frequency shift: +FSK or ASK-RX Default 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0
Table 2-17 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Sub Address 02H: XTAL_TUNING Function Value Description not used not used not used not used not used not used not used not used not used not used Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Nominal_Frequ_5 Nominal_Frequ_4 Nominal_Frequ_3 Nominal_Frequ_2 Nominal_Frequ_1 Nominal_Frequ_0
8pF 4pF 2pF 1pF 500fF 250fF
Setting for nominal frequency ASK-TX FSK-RX
Table 2-19 Table 2-18 Bit D7 D6 D5 D4 D3 D2 D1 D0 Sub Address 03H: LPF Function Datafilter_3 Datafilter_2 Datafilter_1 Datafilter_0 IQ_Filter_2 IQ_Filter_1 IQ_Filter_0 not used 3dB cutoff frequency of IQ-filter 3dB cutoff frequency of data filter Description Default 0 0 0 1 1 0 0 0 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Sub Addresses 04H / 05H: ON/OFF_TIME Function ON_15 / OFF_15 ON_14 / OFF_14 ON_13 / OFF_13 ON_12 / OFF_12 ON_11 / OFF_11 ON_10 / OFF_10 ON_9 / OFF_9 ON_8 / OFF_8 ON_7 / OFF_7 ON_6 / OFF_6 ON_5 / OFF_5 ON_4 / OFF_4 ON_3 / OFF_3 ON_2 / OFF_2 ON_1 / OFF_1 ON_0 / OFF_0 Default ON_TIME 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 Default OFF_TIME 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0
Table 2-20 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Sub Address 06H: COUNT_TH1 Function not used not used not used not used TH1_11 TH1_10 TH1_9 TH1_8 TH1_7 TH1_6 TH1_5 TH1_4 TH1_3 TH1_2 TH1_1 TH1_0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 2-21 Bit Sub Address 07H: COUNT_TH2 Function Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
not used not used not used not used TH2_11 TH2_10 TH2_9 TH2_8 TH2_7 TH2_6 TH2_5 TH2_4 TH2_3 TH2_2 TH2_1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Preliminary Specification
28
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TDA5255 E1 Version 1.1
Confidential Functional Description
Table 2-22 Bit D7 D6 D5 D4 D3 D2 D1 D0
Sub Address 08H: RSSI_TH3 Function not used SELECT TH3_5 TH3_4 TH3_3 TH3_2 TH3_1 TH3_0 Table 2-24 Bit D7 D6 D5 D4 D3 D2 D1 D0 FSK-Ramp 0 FSK-Ramp 1 Bipolar_FET 0= VCC, 1= RSSI Description Default 1 1 1 1 1 1 1 1
Table 2-23 Bit D7 D6 D5 D4 D3 D2 D1 D0
Sub Address 0DH: CLK_DIV Function not used not used DIVMODE_1 DIVMODE_0 CLKDIV_3 CLKDIV_2 CLKDIV_1 CLKDIV_0 Default 0 0 0 0 1 0 0 0
Sub Address 0EH: XTAL_CONFIG Function Description not used not used not used not used not used only in bipolar mode 0= FET, 1=Bipolar Default 0 0 0 0 0 0 0 1
Table 2-25 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Sub Address 0FH: BLOCK_PD Function REF_PD RC_PD WINDOW_PD ADC_PD PEAK_DET_PD DATA_SLIC_PD DATA_FIL_PD QUAD_PD LIM_PD I/Q_FIL_PD MIX2_PD MIX1_PD LNA_PD PA_PD PLL_PD XTAL_PD Description 1= power down Band Gap Reference 1= power down RC Oscillator 1= power down Window Counter 1= power down ADC 1= power down Peak Detectors 1= power down Data Slicer 1= power down Data Filter 1= power down Quadri Correlator 1= power down Limiter 1= power down I/Q Filters 1= power down I/Q Mixer 1= power down 1st Mixer 1= power down LNA 1= power down Power Amplifier 1= power down PLL 1= power down XTAL Oscillator Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 2-26 Bit D7 D6 D5 D4 D3 D2 D1 D0
Sub Address 80H: STATUS Function COMP_LOW COMP_IN COMP_HIGH Description 1 if data rate < TH1 1 if TH1 < data rate < TH2 1 if TH2 < data rate 1 if data rate < 0,5*TH1 1 if 0,5*TH1 < data rate < 0,5*TH2 1 if 0,5*TH2 < data rate 1 if RSSI value is equal TH3 1 if RSSI value is greater than TH3
Table 2-27 Bit D7 D6 D5 D4 D3 D2 D1 D0 Function PD_ADC SELECT RSSI_5 RSSI_4 RSSI_3 RSSI_2 RSSI_1 RSSI_0
Sub Address 81H: ADC Description ADC power down feedback Bit SELECT feedback Bit RSSI value Bit5 RSSI value Bit4 RSSI value Bit3 RSSI value Bit2 RSSI value Bit1 RSSI value Bit0
COMP_0,5*LOW COMP_0,5*IN COMP_0,5*HIGH RSSI=TH3 RSSI>TH3
Preliminary Specification
29
2002-11-28
TDA5255 E1 Version 1.1
Confidential Functional Description
2.4.16
Wakeup Logic
SLAVE M O DE (d e fa ult)
MODE_1 = 0 MODE_2 = 0
S E L F P O L L IN G M ODE
MODE_1 = 1 MODE_2 = X
T IM E R M O D E
MODE_1 = 0 MODE_2 = 1
3_modes.wmf
Figure 2-9
Wakeup Logic States
Table 2-28 MODE settings: CONFIG register MODE_1 MODE_2 0 0 0 1 1 X
Mode SLAVE MODE TIMER MODE SELF POLLING MODE
SLAVE MODE: The receive and transmit operation is fully controlled by an external control device via the respective RxTx, AskFsk, PwdDD, and Data pins. The wakeup logic is inactive in this case. After RESET or 1st Power-up the chip is in SLAVE MODE. By setting MODE_1 and MODE_2 in the CONFIG register the mode may be changed. SELF POLLING MODE: The chip turns itself on periodically to receive using a built-in 32kHz RC oscillator. The timing of this is determined by the ON_TIME and OFF_TIME registers, the duty cycle can be set between 0 and 100% in 31.25s increments. The data detect logic is enabled and a 15s LOW impulse is provided at PwdDD pin (Pin 27), if the received data is valid.
ON_TIME OFF_TIME ON_TIME
Action
RX ON: valid Data
RX ON: invalid Data
t
PwdDD pin in SELF POLLING MODE
min. 2.6ms
t 15s
timing_selfpllmode.wmf
Figure 2-10
Timing for Self Polling Mode (ADC & Data Detect in one shot mode) 30 2002-11-28
Preliminary Specification
TDA5255 E1 Version 1.1
Confidential Functional Description
Note: The time delay between start of ON time and the 15s LOW impulse is 2.6ms + 3 period of data rate. If ADC & Data Detect Logic are in continuous mode the 15s LOW impulse is applied at PwdDD after each data valid decision. In self polling mode if D9=0 (Register 00h) and when PwdDD pin level is HIGH the CLK output is on during ON time and off during OFF time. If D9=1, the CLK output is always on. TIMER MODE: Only the internal Timer (determined by the ON_TIME and OFF_TIME registers) is active to support an external logic with periodical Interrupts. After ON_TIME + OFF_TIME a 15s LOW impulse is applied at the PwdDD pin (Pin 27).
ON_TIME OFF_TIME ON_TIME
Action
Register 04H
Register 05H
Register 04H
t
PwdDD pin in TIMER MODE 15s 15s
t
timing_timermode.wmf
Figure 2-11
Timing for Timer Mode
Please note to add a serial resistor in the VDD supply line as mentioned on page 13 and in Section 4.4
2.4.17
Data Valid Detection, Data Pin
Data signals generate a typical spectrum and this can be used to determine if valid data is on air.
Amplitude
Frequency & RSSI Window DATA on air
RSSI
no DATA on air Frequency f
data_rate_detect.wmf
Figure 2-12
Frequency and RSSI Window
The "data valid" criterion is generated from the result of RSSI-TH3 comparison and tGATE between TH1 and TH2 result as shown below. In case of Manchester coding the 0,5*TH1 and 0,5*TH2 gives improved performance.
Preliminary Specification
31
2002-11-28
TDA5255 E1 Version 1.1
Confidential Functional Description
The use of permanent data valid recognition makes it absolutely necessary to set the RSSI-ADC and the Window counter into continuous mode (Register 00H, Bit D5 = D6 = 1).
0,5*TH1
TGATE
0,5*TH2 TH2 TH3 DATA VALID
TH1
TGATE RSSI
data_valid.wmf
Figure 2-13
Data Valid Circuit
D_OUT and RX_DATA_INV from the CONFIG register determine the output of data at Pin 28. RxTxint and TX_ON are internally generated signals. In RX and power down mode Data pin (Pin 28) is tied to GND.
RxTxint RX_DATA_INV RX DATA DATA VALID D_OUT TX DATA Data 28
TX ON
data_switch.wmf
Figure 2-14
Data Input/Output Circuit
2.4.18
Sequence Timer
The sequence timer has to control all the enable signals of the analog components inside the chip. The time base is the 32 kHz RC oscillator. After the first POWER ON or RESET a 1 MHz clock is available at the clock output pin. This clock output can be used by an external mP to set the system into the desired state and outputs valid data after 500 s (see Figure 2-15 and Figure 2-16, tCLKSU) There are two possibilities to start the device after a reset or first power on: PWDDD pin is LOW: Normal operation timing is performed after tSYSSU (see Figure 2-15). PWDDD pin is HIGH (device in power down mode): A clock is offered at the clock output pin until the device is activated (PWDDD pin is pulled to LOW). After the first activation the time tSYSSU is required until normal operation timing is performed (see Figure 2-16 ). This could be used to extend the clock generation without device programming or activation.
Preliminary Specification
32
2002-11-28
TDA5255 E1 Version 1.1
Confidential Functional Description
Note: It is required to activate the device for the duration of tSYSSU after first power on or a reset. Only if this is done the normal operation timing is performed. With default settings the clock generating units are disabled during PD, therefore no clock is available at the clock output pin. It is possible to offer a clock signal at the clock output pin every time (also during PD) if the CLK_EN Bit in the CONFIG register is set to HIGH.
RESET or 1st POWER ON PWDDD = low
STATUS XTAL EN DC OFFSET COMPENSATION PEAK DETECTOR EN DATADETECTION EN POWER AMP EN
TX activ or RX activ
CLOCK FOR EXTERNAL P if RX if RX if RX if TX
PD
TX activ
PD
RX activ
TX activ
RX activ
t C LK S U
0.5ms 0.5ms
tC L K S U
0.5ms
t C LK S U
1.1ms
tT X S U
t TX S U
1.1ms
t TX S U tR X S U
2.2ms
1.1ms
tS Y S S U
8ms
tR X S U
2.2ms
tR X S U
2.2ms
tD D S U
2.6ms
tD D S U
2.6ms
tD D S U
2.6ms
Sequenzer_Timing_pupstart.wmf
Figure 2-15
1st start or reset in active mode
Note: The time values are typical values
RESET or 1st POWER ON PWDDD = high
PWDDD = low
STATUS XTAL EN DC OFFSET COMPENSATION PEAK DETECTOR EN DATADETECTION EN POWER AMP EN
PD
CLOCK FOR EXTERNAL P
TX activ or RX activ
PD
TX activ
RX activ
if RX if RX if RX if TX 0.5ms
t C LK S U t TX S U
1.1ms
0.5ms
t C L KS U
1.1ms
t TX S U
tS Y S S U
8ms
tRXSU t R X SU
2.2ms
2.2ms
tDDSU
2.6ms
tD D S U
2.6ms
Sequenzer_Timing_pdstart.wmf
Figure 2-16
1st start or reset in PD mode
Preliminary Specification
33
2002-11-28
TDA5255 E1 Version 1.1
Confidential
Note: The time values are typical values This means that the device needs tDDSU setup time to start the data detection after RX is activated. When activating TX it requires tTXSU setup time to enable the power amplifier. For timing information refer to Table 4-3. For Test purposes a TESTMODE is provided by the Sequencer as well. In this mode the BLOCK_PD register be set to various values. This will override the Sequencer timing. Depending on the settings in Config Register 00H the corresponding building blocks are enabled, as shown in the subsequent figure.
Functional Description
RESET 32 kHz RX ON TX ON ASK/FSK
RC- OSC.
TIMING DECODE
2 16
XTAL FREQU. SELECT ENABLE / DISABLE BUILDING BLOCKS
SWITCH
16 TESTMODE ALL_PD CLK_EN
16
INTERNAL BUS
BLOCK_PD REGISTER
sequencer_raw.wmf
Figure 2-17
Sequencer`s capability
2.4.19
Clock Divider
It supports an external logic with a programmable Clock at pin 26 (CLKDIV).
INTERNAL BUS DIVMODE_0 DIVMODE_1
18 MHz
4 BIT COUNTER
DIVIDE BY 2
32 kHz WINDOW COUNT COMPLETE
SWI CH T
CLKDiv 26
clk_div.wmf
Figure 2-18
Clock Divider
The Output Selection and Divider Ratio can be set in the CLK_DIV register.
Preliminary Specification
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Confidential Functional Description
Table 2-29 D5 0 0 1 1
CLK_DIV Output Selection D4 0 1 0 1
Output Output from Divider (default) 18.089MHz 32kHz Window Count Complete
Note: Data are valid 500 s after the crystal oscillator is enabled (see Figure 2-15 and Figure 216, tCLKSU). Table 2-30 CLK_DIV Setting D3 D2 D1 D0 Total Divider Ratio 0 0 0 0 2 0 0 1 4 0 0 0 1 0 6 0 0 1 1 8 0 1 0 0 10 0 1 0 1 12 0 1 1 0 14 1 1 1 16 0 1 0 0 0 18 1 0 0 1 20 1 0 1 0 22 1 0 1 1 24 1 1 0 0 26 1 0 1 28 1 1 1 1 0 30 1 1 1 1 32
Output Frequency [MHz] 9,0 4,5 3,0 2,25 1,80 1,50 1,28 1,125 1,00 (default) 0,90 0,82 0,75 0,69 0,64 0,60 0,56
Note: As long as default settings are used, there is no clock available at the clock output during Power Down. It is possible to enable the clock during Power Down by setting CLK_EN (Bit D9) in the Config Register (00H) to HIGH.
2.4.20
RSSI and Supply Voltage Measurement
The input of the 6Bit-ADC can be switched between two different sources: the RSSI voltage (default setting) or a resistor network dividing the Vcc voltage by 5. Table 2-31 Source for 6Bit-ADC Selection (Register 08H) SELECT Input for 6Bit-ADC Vcc / 5 0 1 RSSI (default)
Preliminary Specification
35
2002-11-28
TDA5255 E1 Version 1.1
Confidential Functional Description
To prevent wrong interpretation of the ADC information (read from Register 81H: ADC) you can use the ADC- Power Down feedback Bit (D7) and the SELECT feedback Bit (D6) which correspond to the actual measurement. Note: As shown in Section 2.4.18 there is a setup time of 2.6ms after RX activating. Thus the measurement of RSSI voltage does only make sense after this setup time.
Preliminary Specification
36
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3
3.1 3.1.1
Application
LNA and PA Matching RX/TX Switch
RX/TX_Switch.wmf
Figure 3-1
RX/TX Switch
The RX/TX-switch combines the PA-output and the LNA-input into a single 50 Ohm SMAconnector. Two pin-diodes are used as switching elements. If no current flows through a pin diode, it works as a high impedance for RF with very low capacitance. If the pin-diode is forward biased, it provides a low impedance path for RF. (some W)
3.1.2
Switch in RX-Mode
The RX/TX-switch is set to the receive mode by either applying a high level or an open to the RX/ TX-jumper on the evalboard or by leaving it open. Then both pin-diodes are not biased and therefore have a high impedance.
Preliminary Specification
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RX_Mode.wmf
Figure 3-2
RX-Mode
The RF-signal is able to run from the RF-input-SMA-connector to the LNA-input-pin LNI via C1, C2, C7, L3 and C9. R1 does not affect the matching circuit due to its high resistance. The other input of the differential LNA LNIX can always be AC-grounded using a large capacitor without any loss of performance. In this case the differential LNA can be used as a single ended LNA, which is easier to match. The S11 of the LNA at pin LNI on the evalboard is 0.94 / -23 (equals a resistor of 1.67kOhm in parallel to a capacitor of 1.5pF) for both high and low-gain-mode of the LNA. (pin LNIX AC-grounded) This impedance has to be matched to 50 Ohm with the parts C9, L3, C7 and C2. C1 is a DC-decoupling-capacitor. On the evalboard the most important matching components are (shunt) L3 and (series)C7, C2. The capacitors is mainly a DC-decoupling-capacitor and may be used for some fine tuning of the matching circuit. A good CAE tool (featuring smith-chart) may be used for the calculation of the values of the components. However, the final values of the matching components always have to be found on the board because of the parasitics of the board, which highly influence the matching circuit at RF.
Preliminary Specification
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Measured Magnitude of S11 of evalboard:
Application
S11_measured_434.pcx.
Figure 3-3
S11 measured
Above you can see the measured S11 of the evalboard. The -3dB-points are at 404MHz and 468MHz. So the 3dB-bandwidth is:
[3 - 1]
B = fU - f L = 468MHz - 404 MHz = 64MHz The loaded Q of the resonant circuit is: 434,2MHz f QL = center = = 6,8 B 64 MHz
[3 - 2]
The unloaded Q of the resonant circuit is equal to the Q of the inductor due to its losses.
QU = QINDUCTOR 32@ 434MHz
[3 - 3]
An approximation of the losses of the input matching network can be made with the formula:
e Qu e 6,8 u LOSS = -20 * log e1 - L u = -20 * log e1 u = 2dB QU u 32 u e e e u
[3 - 4]
Preliminary Specification
39
2002-11-28
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Confidential Application
The noise figure of the LNA-input-matching network is equal to its losses. The input matching network is always a compromise of sensitivity and selectivity. The loaded Q should not get too high because of 2 reasons: more losses in the matching network and hence less sensitivity tolerances of components affect matching too much. This will cause problems in a tuning-free mass production of the application. A good CAE-tool will help to see the effects of component tolerances on the input matching more accurate by tweaking each value. A very high selectivity can be reached by using SAW-filters at the expense of higher cost and lower sensitivity which will be reduced by the losses of the SAW-Filter of approx. 4dB. Image-suppression: Due to the quite high 1st-IF of the frontend, the image frequency is quite far away. The image frequency of the receiver is at:
f IMAGE = f SIGNAL + 2 * f IF = 434,2 MHz + 2 *144,7 = 723,7 MHz
The image suppression on the evalboard is about 16dB. LO-leakage: The LO of the 1st Mixer is at:
4 4 = 434,2MHz * = 578,9MHz 3 3
[3 - 5]
f LO = f RECEIVE *
[3 - 6]
The LO-leakage of the evalboard on the RF-input is about -102dBm. This is far below the ETSIradio-regulation-limit for LO-leakage.
3.1.3
Switch in TX-Mode
The evalboard can be set into the TX-Mode by grounding the RX/TX-jumper on the evalboard or programming the TDA5255 to operate in the TX-Mode. If the IC is programmed to operate in the TX-Mode, the RX/TX-pin will act as an open drain output at a logical LOW. Then a DC-current can flow from VCC to GND via L1, L2, D1, R1 and D2.
I PIN
Vcc 2 V FORWARD , PIN
DIODE
DIODE
R1
[3 - 7]
Preliminary Specification
40
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Now both pin-diodes are biased with a current of approx. 0.3mA@3V and have a very low impedance for RF.
TX_Mode.wmf
Figure 3-4
TX_Mode
R1 does not influence the matching because of its very high resistance. Due to the large capacitance of C1, C6 and C5 the circuit can be further simplified for RF:
TX_Mode_simplified.wmf
Figure 3-5
TX_Mode_simplified
The LNA-matching is RF-grounded now, so no power is lost in the LNA-input. The PA-matching consists of C2, C3 L2, C4 and L1. When designing the matching of the PA, C2 must not be changed anymore because its value is already fixed by the LNA-input-matching. Preliminary Specification 41 2002-11-28
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Confidential Application
3.1.4
Power-Amplifier
The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of q<VS L C RL
Equivalent_power_wmf.
Figure 3-6
Equivalent power amplifier tank circuit
The optimum load at the collector of the power amplifier for "critical" operation under idealized conditions at resonance is:
RLC
VS 2 2PO
[3 - 8]
A typical value of RLC for an RF output power of Po= 13mW is:
RLC =
32 = 350W 2 * 0.013
[3 - 9]
Critical" operation is characterized by the RF peak voltage swing at the collector of the PA transistor to just reach the supply voltage VS. The high efficiency under "critical" operating conditions can be explained by the low power loss at the transistor. During the conducting phase of the transistor there is no or only a very small collector voltage present, thus minimizing the power loss of the transistor (iC*uCE). This is particularly true for low current flow angles of q< RLC. As shown in Figure 3-7, however, power efficiency E (and bandwidth) will increase by some degree when operating at higher RL. The collector efficiency E is defined as Preliminary Specification 42 2002-11-28
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PO VS I C
Application
E
[3 - 10]
The diagram of Figure 3-7 has been measured directly at the PA-output at VS=3V. A power loss in the matching circuit of about 3dB will decrease the output power. As shown in the diagram, 250 Ohm is the optimum impedance for operation at 3V. For an approximation of ROPT and POUT at other supply voltages those 2 formulas can be used:
[3 - 11]
ROPT ~ VS
and
POUT ~ ROPT
[3 - 12]
Power_E_vs_RL_434.wmf
Figure 3-7
Output power Po (mW) and collector efficiency E vs. load resistor RL.
The DC collector current Ic of the power amplifier and the RF output power Po vary with the load resistor RL. This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of "overcritical" operation. The depth of this dip will increase with higher values of RL. As Figure 3-8 shows, detuning beyond the bandwidth of the matching circuit results in a significant increase of collector current of the power amplifier and in some loss of output power. This diagram shows the data for the circuit of the test board at the frequency of 434MHz. The effective load resistor of this circuit is RL= 250Ohm, which is the optimum impedance for operation at 3V. This will lead to a dip of the collector current f approx. 20%.
Preliminary Specification
43
2002-11-28
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Confidential Application
pout_vs_frequ_434.wmf
Figure 3-8
Power output and collector current vs. frequency
C4, L2 and C3||C2 are the main matching components which are used to transform the 50 Ohm load at the SMA-RF-connector to a higher impedance at the PA-output (250Ohm@3V). L1 can be used for finetuning of the resonance frequency but should not be too low in order to keep its loss low. The transformed impedance of 250Ohm+j0 at the PA-output-pin can be verified with a network analyzer using this measurement procedure: 1. Calibrate your network analyzer. 2. Connect a short, low-loss 50 Ohm cable to your network analyzer with an open end on one side. Semirigid cable works best. 3. Use the Port Extension" feature of your network analyzer to shift the reference plane of your network analyzer to the open end of the cable. 4. Connect the center-conductor of the cable to the solder pad of the pin PA" of the IC. The shield has to be grounded. Very short connections must be used. Do not remove the IC or any part of the matching-components! 5. Screw a 50Ohm-dummy-load on the RF-I/O-SMA-connector 6. The TDA5255 has to be in ASK-TX-Mode, Data-Input=LOW. 7. Be sure that your network analyzer is AC-coupled and turn on the power supply of the IC. 8. Measure the S-parameter
Preliminary Specification
44
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Sparam_measured_434.pcx
Figure 3-9
Sparam_measured_200M
Above you can see the measurement of the evalboard with a span of 200MHz. The evalboard has been optimized for 3V. The load is about 250+j0 at 434,2MHz. A tuning-free realization requires a careful design of the components within the matching network. A simple linear CAE-tool will help to see the influence of tolerances of matching components. Suppression of spurious harmonics may require some additional filtering within the antenna matching circuit. Both can be seen in Figure 3-10 and Figure 3-11 The total spectrum of the evalboard can be summarized as:
Carrier fc fc-18.1MHz fc+18.1MHz 2nd harmonic 3rd harmonic
+9dBm -71dBm -71dBm -45dBm -48dBm
Preliminary Specification
45
2002-11-28
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Confidential Application
spectrum1.bmp
Figure 3-10
Transmit Spectrum 3GHz
spektrum2.bmp
Figure 3-11
Transmit Spectrum 300MHz
Regarding CEPT ERC recommendation 70-03 and ETSI regulation EN 300220 both of the following figures show full compliance in case of ASK and FSK modulation spectrum. Data signal is a Manchester encoded PRBS9 (Pseudo Random Binary Sequence), RF output power is +9dBm at a supply voltage of 3V. With these settings ASK allows a maximum data rate of 100kBaud and FSK can handle with up to 32kBaud, both Manchester encoded. See also Section 4.1.4
Preliminary Specification
46
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ASK_100kBaud_Manch_PRBS9_9dBm_3V_Spectrum_CEPT_ERC7003.wmf
Figure 3-12
ASK Transmit Spectrum 100kBaud, Manch, PRBS9, 9dBm, 3V
FSK_32kBaud_Manch_PRBS9_9dBm_3V_Spectrum_CEPT_ERC7003.wmf
Figure 3-13
FSK Transmit Spectrum 32kBaud, Manch, PRBS9, 9dBm, 3V
Preliminary Specification
47
2002-11-28
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3.2
Crystal Oscillator
The equivalent schematic of the crystal with its parameters specified by the crystal manufacturer can be taken from the subsequent figure. Here also the load capacitance of the crystal CL, which the crystal wants to see in order to oscillate at the desired frequency, can be seen.
L1
C1
R1
CL
-R
C0
Crystal.wmf
Figure 3-14
Crystal L1: C1: C0: motional inductance of the crystal motional capacitance of the crystal shunt capacitance of the crystal
Therefore the Resonant Frequency fs of the crystal is defined as:
1 2p L1 * C1
fS =
[3 - 13]
The Series Load Resonant Frequency fS` of the crystal is defined as:
f S =
1 2p L1 * C1
* 1+
C1 C0 + C L
[3 - 14]
regarding Figure 3-14 fs' is the nominal frequency of the crystal with a specified load when tested by the crystal manufacturer. Pulling Sensitivity of the crystal is defined as the magnitude of the relative change in frequency relating to the variation of the load capacitor.
Preliminary Specification
48
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Confidential Application
df S - C1 fS dD = = 2 dC L dCL 2(C0 + C L )
[3 - 15]
Choosing CL as large as possible results in a small pulling sensitivity. On the other hand a small CL keeps the influence of the serial inductance and the tolerances associated to it small (see formula [3-17]). Start-up Time
t Start ~
L1 - R - Rext
where: -R: Rext:
[3 - 16]
is the negative impedance of the oscillator see Figure 3-15 is the sum of all external resistances (e.g. R1 or any other resistance that may be present in the circuit, see Figure 3-14
The proportionality of L1 and C1 of the crystal is defined by formula [3-13]. For a crystal with a small C1 the start -up time will also be slower. Typically the lower the value of the crystal frequency, the lower the C1. A short conclusion regarding crystal and crystal oscillator dependencies is shown in the following table:
Table 3-1
Crystal and crystal oscilator dependency Result Relative Tolerance Maximum Deviation >> >> < < >>> > >> > > < tStart-up < << -
Independent variable C1 > C0 > frequency of quartz > LOSC > CL >
The crystal oscillator in the TDA5255 is a NIC (negative impedance converter) oscillator type. The input impedance of this oscillator is a negative impedance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv as shown in formula [3-17].
Preliminary Specification
49
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Confidential Application
-R
LOSC
f, CL
CV
TDA 5250
QOSZ_NIC.wmf
Figure 3-15
Crystal Oscillator
CL =
1 1 CV = 1 1 - w 2 LOSC + w 2 LOSC CV CL
CL: w: LOSC:
[3 - 17]
crystal load capacitance for nominal frequency angular frequency inductivity of the crystal oscillator - typ: 2.7mH with pad of board 2.45H without pad
With the aid of this formula it becomes obvious that the higher the serial capacitance CV is, the higher is the influence of LOSC. The tolerance of the internal oscillator inductivity is much higher, so the inductivity is the dominating value for the tolerance. FSK modulation and tuning are achieved by a variation of Cv. In case of small frequency deviations (up to +/- 1000 ppm), the desired load capacitances for FSK modulation are frequency depending and can be calculated with the formula below.
2 x ( C + C )o Df ae 0 L C L - C 0 x ---------- x c 1 + ---------------------------------/ + Nxf e C o 1 C L = ----------------------------------------------------------------------------------------2 x ( C 0 + C L )o Df ae 1 ---------- x c 1 + ---------------------------------/ Nxf e C1 o
[3 - 18]
CL: C0: C1: f: N: Df:
crystal load capacitance for nominal frequency shunt capacitance of the crystal motional capacitance of the crystal crystal oscillator frequency division ratio of the PLL peak frequency deviation
Preliminary Specification
50
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Confidential Application
With CL+ and CL- the necessary Cv+ for FSK HIGH and Cv- for FSK LOW can be calculated. Alternatively, an external AC coupled (10nF in series to 1kW) signal can be applied at pin 19 (Xout). The drive level should be approximately 100mVpp.
3.2.1
Synthesizer Frequency setting
Generating ASK and FSK modulation 3 setable frequencies are necessary.
3.2.1.1
Possible crystal oscillator frequencies
The resulting possible crystal oscillator frequencies are shown in the following Figure 3-16
RX: TX: FSK ASK ASK FSK+
FSK-
Deviation
Deviation
f1
f0
Nominal Frequency
f2
free_reg.wmf
Figure 3-16
possible crystal oscillator frequencies
In ASK receive mode the crystal oscillator is set to frequency f2 to realize the necessary frequency offset to receive the ASK signal at f0*N (N: division ratio of the PLL). To set the 3 different frequencies 3 different Cv are necessary. Via internal switches 3 external capacitors can be combined to generate the necessary Cv in case of ASK- or FSK-modulation. Internal banks of switchable capacitors allow the finetuning of these frequencies.
3.2.2
Transmit/Receive ASK/FSK Frequency Assignment
Depending on whether the device operates in transmit or receive mode or whether it operates in ASK or FSK the following cases can be distinguished:
3.2.2.1
FSK-mode
In transmit mode the two frequencies representing logical HIGH and LOW data states have to be adjusted depending on the intended frequency deviation and separately according to the following formulas: fCOSC HI = (fRF + fDEV) / 24 fCOSC LOW = (fRF - fDEV) / 24
[3 - 19]
Preliminary Specification
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e.g. fCOSC HI fCOSC LOW = (434,16E6 + 35E3) / 24= 18.09146MHz = (434,16E6 - 35E3) / 24= 18.08854MHz
Application
with a frequency deviation of 35kHz. Figure 3-17 shows the configuration of the switches and the capacitors to achieve the 2 desired frequencies. Gray parts of the schematics indicate inactive parts. For FSK modulation the ASKswitch is always open. For FSK LOW the FSK-switch is closed and Cv2 and Ctune2 are bypassed. The effective Cv- is given by:
CV - = C v1 + C tune1
[3 - 20]
For finetuning Ctune1 can be varied over a range of 8 pF in steps of 125fF. The switches of this Cbank are controlled by the bits D0 to D5 in the FSK register (subaddress 01H, see Table 3-6). For FSK HIGH the FSK-switch is open. So the effective Cv+ is given by:
( C v1 + C tune1 ) x ( C v2 + C tune2 ) C v+ = -------------------------------------------------------------------------------------C v1 + C tune1 + C v2 + C tune2
[3 - 21]
The C-bank Ctune2 can be varied over a range of 16 pF in steps of 250fF for finetuning of the FSK HIGH frequency. The switches of this C-bank are controlled by the bits D8 to D13 in the FSK register (subaddress 01H, see Table 3-6).
XOUT 19 f, CL XIN 21 CV1 XSWF 20 XSWA 22 CV2 CV3 XGND 23 ASKswitch
L
-R
XOUT 19 f, CL XIN 21 CV1
L
-R
Ctune1
XSWF 20 XSWA 22 CV2 CV3 XGND 23 ASKswitch
Ctune1
Ctune2 FSKswitch
Ctune2 FSKswitch
QOSC_FSK.wmf
FSK LOW
FSK HIGH
Figure 3-17
FSK modulation 52 2002-11-28
Preliminary Specification
TDA5255 E1 Version 1.1
Confidential Application
In receive mode the crystal oscillator frequency is set to yield a direct-to-zero conversion of the receive data. Thus the frequency may be calculated as fCOSC = fRF / 24, e.g. fCOSC = 434,16E6 / 24= 18.09MHz which is identical to the ASK transmit case.
XOUT 19 f, CL XIN 21 CV1 XSWF 20 XSWA 22 CV2 CV3 XGND 23 ASKswitch Ctune2 FSKswitch Ctune1 L -R
[3 - 22]
QOSC_ASK.wmf
Figure 3-18
FSK receive
In this case the ASK-switch is closed. The necessary Cvm is given by:
( C v1 + C tune1 ) x ( C v2 + C + C tune2 ) v3 C vm = ------------------------------------------------------------------------------------------------------C v1 + C tune1 + C v2 + C + C tune2 v3
[3 - 23]
The C-bank Ctune2 can be varied over a range of 16 pF in steps of 250fF for finetuning of the FSK receive frequency. In this case the switches of the C-bank are controlled by the bits D0 to D5 of the XTAL_TUNING register (subaddress 02H, see Table 3-5).
3.2.2.2
ASK-mode:
In transmit mode the crystal oscillator frequency is the same as in the FSK receive case, see Figure 3-18. In receive mode a receive frequency offset is necessary as the limiters feedback is AC-coupled. This offset is achieved by setting the oscillator frequency to the FSK HIGH transmit frequency, see Figure 3-17.
3.2.3
Parasitics
For the correct calculation of the external capacitors the parasitic capacitances of the pins and the switches (C20, C21, C22) have to be taken into account. Preliminary Specification 53 2002-11-28
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Confidential Application
XOUT 19 f, CL XIN 21 CV1 XSWF 20 XSWA 22 CV2 CV3 XGND 23
L
-R
C21
Ctune1
C22
C20
Ctune2
QOSC_parasitics.wmf
Figure 3-19
parasitics of the switching network
Table 3-2
Typical values of parasitic capacitances Name Value C20 4,6 pF C21 FSK-: 2,8 pF / FSK+&ASK: 2.2pF C22 1 pF
With the given parasitics the actual Cv can be calculated:
C =C +C +C
[3 - 24] [3 - 25]
v-
v1
tune1
21
C
( C v1 + C tune1 ) x ( C v2 + C 20 + C ) tune2 = ------------------------------------------------------------------------------------------------------- + C 21 v+ C +C +C +C +C v1 tune1 v2 20 tune2
C
(C + C ) x (C + C + C + C + C ) v1 tune1 v2 20 22 v3 tune2 = ---------------------------------------------------------------------------------------------------------------------------------------- + C 21 vm C v1 + C tune1 + C v2 + C 20 + C + C 22 + C v3 tune2
[3 - 26]
Note: Please keep in mind also to include the Pad parasitics of the circuit board.
Preliminary Specification
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3.2.4
Calculation of the external capacitors
e.g. fFSK- = fCOSC LOW
1. Determination of necessary crystal frequency using formula [3-19]. 2. Determine corresponding CLoad applying formula [3-18]. e.g. CL FSK- = CL 3. Necessary CV using formula [3-17]. e.g.
CV - =
1 1 C L , FSK + (2pf FSK - ) * LOSC
2
1. When the necessary Cv for the 3 frequencies (Cv- for FSK LOW, Cv+ for FSK HIGH and Cvm for FSK-receive) are known the external capacitors and the internal tuning caps can be calculated using the following formulas:
-FSK:
C v1 + C tune1 = C v- - C 21 ( C v1 + C tune1 ) x ( C v+ - C 21 ) C v2 + C tune2 = --------------------------------------------------------------------- - C 20 ( C v1 + C tune1 ) - ( C v+ - C 21 ) ( C v1 + C tune1 ) x ( C vm - C 21 ) C v3 + C tune2 = ------------------------------------------------------------------------ - C 20 - C v2 - C 22 ( C v1 + C tune1 ) - ( C vm - C 21 )
[3 - 27] [3 - 28]
+FSK: FSK_RX:
[3 - 29]
To compensate frequency errors due to crystal and component tolerance Cv1, Cv2 and Cv3 have to be varied. To enable this correction, half of the necessary capacitance variation has to be realized with the internal C-banks. If no finetuning is intended it is recommended to leave XIN (Pin 21) open. So the parasitic capacitance of Pin 21 has no effect. Note: Please keep in mind also to include the Pad parasitics of the circuit board. In the suitable range for the serial capacitor, either capacitors with a tolerance of 0.1pF or 1% are available. A spreadsheet, which can be used to predict the total frequency error by simply entering the crystal specification, may be obtained from Infineon.
3.2.5
FSK-switch modes
The FSK-switch can be used either in a bipolar or in a FET mode. The mode of this switch is controlled by bit D0 of the XTAL_CONFIG register (subaddress 0EH). In the bipolar mode the FSK-switch can be controlled by a ramp function. This ramp function is set by the bits D1 and D2 of the XTAL_CONFIG register (subadress 0EH). With these modes of the FSK-switch the bandwidth of the FSK spectrum can be influenced. When working in the FET mode the power consumption can be reduced by about 200 mA.
Preliminary Specification
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The default mode is bipolar switch with no ramp function (D0 = 1, D1 = D2 = 0), which is suitable for all bitrates. Table 3-3 Sub Address 0EH: XTAL_CONFIG D0 D1 D2 Switch mode 0 n.a. n.a. FET 1 0 0 bipolar (default) 1 1 0 bipolar 0 1 bipolar 1 1 1 1 bipolar
Ramp time < 0.2 ms < 0.2 ms 4 ms 8 ms 12 ms
Max. Bitrate > 32 kBit/s NRZ > 32 kBit/s NRZ 32 kBit/s NRZ 16 kBit/s NRZ 12 kBit/s NRZ
3.2.6
Finetuning and FSK modulation relevant registers
Case FSK-RX or ASK-TX (Ctune2): Table 3-4 Bit D5 D4 D3 D2 D1 D0 Sub Address 02H: XTAL_TUNING Function Value Nominal_Frequ_5 8pF Nominal_Frequ_4 4pF Nominal_Frequ_3 2pF Nominal_Frequ_2 1pF Nominal_Frequ_1 500fF Nominal_Frequ_0 250fF
Description Setting for nominal frequency ASK-TX FSK-RX (Ctune2)
Default 0 1 0 0 1 0
Case FSK-TX or ASK-RX (Ctune1 and Ctune2): Table 3-5 Bit D13 D12 D11 D10 D9 D8 D5 D4 D3 D2 D1 D0 Sub Address 01H: FSK Function FSK+5 FSK+4 FSK+3 FSK+2 FSK+1 FSK+0 FSK-5 FSK-4 FSK-3 FSK-2 FSK-1 FSK-0
Value 8pF 4pF 2pF 1pF 500fF 250fF 4pF 2pF 1pF 500fF 250fF 125fF
Description Setting for positive frequency shift: +FSK or ASK-RX (Ctune2) Setting for negative frequency shift: -FSK (Ctune1)
Default 0 0 1 0 1 0 0 0 1 1 0 0
Preliminary Specification
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Default values In case of using the evaluation board, the crystal with its typical parameters (fp=18.08958MHz, C1=8fF, C0=2,08pF, CL=20pF) and external capacitors with Cv1=10pF, Cv2=1.8pF, Cv3=15pF each are used the following default states are set in the device. Table 3-6 Default oscillator settings Operating state Frequency ASK-TX / FSK-RX 434.16 MHz +35 kHz +FSK-TX / ASK-RX -FSK-TX -35 kHz
Application
3.2.7
Chip and System Tolerances
Quartz: fp=18.08958MHz; C1=8fF; C0=2,08pF; CL=20pF (typical values) Cv1=10pF, Cv2=1.8pF, Cv3=15pF Table 3-7 Internal Tuning Part Frequency set accuracy Temperature (-40...+85C) Supply Voltage(2.1...5.5V) Total Table 3-8
Frequency tolerance @ 434MHz +/- 1.3kHz +/- 3.5kHz +/- 0.9kHz +/- 5.7kHz
Rel. tolerance +/- 3ppm +/- 8ppm +/- 2ppm +/- 13ppm
Default Setup (without internal tuning & without Pin21 usage) Part Frequency tolerance Rel. tolerance @ 434MHz Internal capacitors (+/- 10%) +/- 3.5kHz +/- 8ppm +/- 10.8kHz +/- 25ppm Inductivity of the crystal oscillator Temperature (-40...+85C) +/- 3.5kHz +/- 8ppm Supply Voltage (2.1...5.5V) +/- 0.9kHz +/- 2ppm Total +/- 18.7kHz +/- 43ppm
Tolerance values in Table 3-8 are valid, if pin 21 is not connected. Establishing the connection to pin 21 the tolerances increase by +/- 27ppm (internal capacitors), if internal tuning is not used. Concerning the frequency tolerances of the whole system also crystal tolerances (tuning tolerances, temperature stability, tolerance of CL) have to be considered. In addition to the chip tolerances also the crystal and external component tolerances have to be considered in the tuning and non-tuning case.
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In case of internal tuning: The crystal on the evaluation board has a temperature stability of +/20ppm (or +/- 8.7kHz), which must be added to the total tolerances in worst case. It's possible to choose a crystal compensating the oscillators temperature drift in a certain range and thus the overall temperature tolerances are minimized. In case of default setup (without internal tuning and without usage of pin 21) the temperature stability and tuning tolerance of the crystal as well as the tolerance of the external capacitors (+/0.1pF) have to be added. The crystal on the evaluation board has a temperature stability of +/20ppm (or +/- 8.7kHz) and a tuning tolerance of +/- 10ppm (or +/- 4.4 kHz). The external capacitors add a tolerance of +/- 3.5ppm (or +/- 1.5kHz). Here also the overall temperature tolerances can be reduced when applying an appropriate temperature drift of the crystal. The frequency stabilities of both the receiver and the transmitter and the modulation bandwidth set the limit for the bandwidth of the IQ filter. To achieve a high receiver sensitivity and efficient suppression of adjacent interference signals, the narrowest possible IQ bandwidth should be realized (see Section 3.3).
3.3
IQ-Filter
The IQ-Filter should be set to values corresponding to the RF-bandwidth of the received RF signal via the D1 to D3 bits of the LPF register (subaddress 03H). Table 3-9 D3 3dB cutoff frequencies I/Q Filter D2 D1 nominal f-3dB in kHz (programmable) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 not used 350 250 200 150 (default) 100 50 not used
resulting effective channel bandwidth in kHz 700 500 400 300 200 100
0 0 0 0 1 1 1 1
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10
50kHz
0
1 00kHz 1 50kHz
-10
200kHz
-2 0
250kHz 350kHz
-3 0
-4 0
-5 0
-6 0
-7 0
-8 0 10 10 0 f [kH z] 10 0 0 10 0 0 0
iq_filter_curve.wmf
Figure 3-20
I/Q Filter Characteristics
effective channel bandwidth
-f
3dB IQ Filter
-f
3dB IQ Filter
f
f
iq_char.wmf
Figure 3-21
IQ Filter and frequency characteristics of the receive system
3.4
Data Filter
The Data-Filter should be set to values corresponding to the bandwidth of the transmitted Data signal via the D4 to D7 bits of the LPF register (subaddress 03H).
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Table 3-10 D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
3dB cutoff frequencies Data Filter D6 D5 D4 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
nominal f-3dB in kHz 5 7 (default) 9 11 14 18 23 28 32 39 49 55 64 73 86 102
3.5
Limiter and RSSI
The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz. Receive Signal Strength Indicator (RSSI) generators are included in both limiters which produce DC voltages that are directly proportional to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI signal.
Cc
CI1x CI1 38
Cc
CQ1x CQ1 37 36
Cc
CI2 CI2x 35 34
Cc
CQ2x CQ2 33 32 31
C
RSSI 29 RSSI
I- Filter fg
I Limiter
Quadr. Corr.
37k
Q- Filter fg
Q Limiter
Quadr. Corr.
limiter input.wmf
Figure 3-22
Limiter and Pinning 60 2002-11-28
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The DC offset compensation needs 2.2ms after Power On or Tx/Rx switch. This time is hard wired and independent from external capacitors CC on pins 31 to 38. The maximum value for this capacitors is 47nF. RSSI accuracy settling time = 2.2ms + 5*RC=2.2ms+5*37k*2.2nF=2.6ms R - internal resistor; C - external capacitor at Pin 29 Table 3-11 Cc [nF] 220 100 47 22 10 Limiter Bandwidth f3dB lower limit [Hz] 100 220 470 1000 2200
f3dB upper limit IQ Filter - ll - ll - ll - ll -
Comment
setup time not guaranteed setup time not guaranteed Eval Board
v [dB]
80
0
f3dB
lower limit
f3dB
IQ Filter
f3dB
Limiter
f
limiter_char.wmf
Figure 3-23
Limiter frequency characteristics
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1300 1200 1100 1000 900 800 RSSI /mV 700 600 500 400 300 200 100 0 -120 -110 -100 -90 -80 -70 RF /dBm -60 -50 -40 -30 -20 high gain low gain
ADC
RSSI.wmf
Figure 3-24
Typ. RSSI Level (Eval Board) @3V
3.6
Data Slicer - Slicing Level
The data slicer is an analog-to-digital converter. It is necessary to generate a threshold value for the negative comparator input (data slicer). The TDA5255 offers an RC integrator and a peak detector which can be selected via logic. Independent of the choice, the peak detector outputs are always active.
3.6.1
Table 3-12 Bit D15
RC Integrator
Sub Address 00H: CONFIG Function Description SLICER 0= LP, 1= Peak Detector
Default 0
SET 0
Necessary external component (Pin14): CSLC This integrator generates the mean value of the data filter output. For a stable threshold value, the cut-off frequency has to be lower than the lowest signal frequency. The cutoff frequency results from the internal resistance R=100kW and the external capacitor CSLC on Pin14. Cut-off frequency:
f
cut - off
=
1 < Min {f 2 p x100 kW x C SLC
Signal
}
[3 - 30]
Component calculation: (rule of thumb) TL - longest period of no signal change
C
SLC
3 xTL 100 k W
[3 - 31]
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DataSlicer
+
Slicer Threshold
Contr. Logic
DATA 28
+ Peak Detector
PDP 13 100k
Data Filter
Signal
100k R - Peak Detector
100k
SLC 14
CSLC
PDN 12
Vcc
SLC_RC.wmf
Figure 3-25
Slicer Level using RC Integrator
3.6.2
Table 3-13 Bit D15
Peak Detectors
Sub Address 00H: CONFIG Function Description SLICER 0= LP, 1= Peak Detector
Default 0
SET 1
The TDA5255 has two peak detectors built in, one for positive peaks in the data stream and the other for the negative ones. Necessary external components: - Pin12: CN - Pin13: CP
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DataSlicer
Application
+
Contr. Logic
DATA 28
Slicer Threshold
+ Peak Detector
PDP 13
Data Filter
Signal
100k R
R1 100k R2 100k
CP
SLC 14 Vcc
- Peak Detector
CN
PDN 12
Vcc
SLC_PkD.wmf
Figure 3-26
Slicer Level using Peak Detector
For applications requiring fast attack and slow release from the threshold value it is reasonable to use the peak detectors. The threshold value is generated by an internal voltage divider. The release time is defined by the internal resistance values and the external capacitors.
t
posPkD
= 100 k W x C p
[3 - 32]
t
Signal
negPkD
= 100 k W x C
n
[3 - 33]
t posPkD
Signal Pos. Peak Detector (pin13)
Threshold SLC(pin14) Neg. Peak Detector (pin12) negPkD t
PkD_timing.wmf
Figure 3-27
Peak Detector timing 64 2002-11-28
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TDA5255 E1 Version 1.1
Confidential
Component calculation: (rule of thumb)
Cp 2 TL1 100k
Application
[3 - 34]
TL1 - longest period of no signal change (LOW signal)
Cn 2 TL2 100k
TL2 - longest period of no signal change (HIGH signal)
[3 - 35]
3.6.3
Peak Detector - Analog output signal
The TDA5255 data output can be digital (pin 28) or in analog form by using the peak detector output and changing some settings. To get an analog data output the slicer must be set to lowpass mode (Reg. 0, D15 = LP = 0) and the peak detector capacitor at pin 12 or 13 has to be changed to a resistor of about 47kOhm.
DataSlicer
+
Slicer Threshold
Contr. Logic
DATA 28
+ Peak Detector
PDP 13 100k 47k
Data Filter
Signal
100k R - Peak Detector
100k
SLC 14
CSLC
PDN 12
Vcc
PkD_analog.wmf
Figure 3-28
Peak Detector as analog Buffer (v=1)
3.6.4
Peak Detector - Power Down Mode
For a safe and fast threshold value generation the peak detector is turned on by the sequencer circuit (see Section 2.4.18) only after the entire receiving path is active. In the off state the output of the positive peak detector is tied down to GND and the output of the negative peak detector is pulled up to VCC.
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Logic
Power Down Mode
0V + Peak Detector
off R1 R2 100k 100k PDP 13 CP SLC 14 Vcc CN PDN 12
Data Filter - Peak Detector
off
Vcc
Vcc
PKD_PWDN.wmff
Figure 3-29
Peak detector - power down mode
Signal Data Signal Vcc Neg. Peak Detector (pin12)
Threshold (pin14)
0 Power ON
Pos. Peak Detector (pin13) Power Down
2,2ms Power ON Peak Detector Power ON t
PkD_PWDN3.wmf
Figure 3-30
Power down mode
3.7
Data Valid Detection
In order to detect valid data two criteria must be fulfilled. One criteria is the data rate, which can be set in register 06h and 07h. The other one is the received RF power level, which can be set in register 08h in form of the RSSI threshold voltage. Thus for using the data valid detection FSK modulation is recommended.
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Timing for data detection looks like the following. Two settings are possible: Continuous" and Single Shot", which can be set by D5 and D6 in register 00H.
Data Sequenzer enables data detection Counter Reset Gate time Compare with single TH and latch result Compare with double TH and latch result (Frequency) Window Count Complete
start of co nve rsio n
t t
re set re se t
t
c ou nt cou nt
t
com p . com p.
t
com p.
t
re ad y* p oss ib le s ta rt o f n ext con ve rsio n
t
Frequ_Detect_Timing_continuous.wmf
Figure 3-31
Frequency Detection timing in continuous mode
Note 1: Chip internal signal Sequencer enables data detection" has a LOW to HIGH transition about 2.6ms after RX is activated (see Figure 2-15). Note 2: The positive edge of the Window Count Complete" signal latches the result of comparison of the analog to digital converted RSSI voltage with TH3 (register 08H). A logic combination of this output and the result of the comparison with single/double THx defines the internal signal data_valid". Figure 3-31 shows that the logic is ready for the next conversion after 3 periods of the data signal. Timing in Single Shot mode can be seen in the subsequent figure:
Data Sequenzer enables data detection Counter Reset Gate time Compare with single TH and latch result Compare with double TH and latch result (Frequency) Window Count Complete
start o f con version
t t
rese t
t
c oun t
t
co m p.
t
com p.
t
re ady * no po ssible s ta rt of n ext c onve rs io n b eca use of S in gle S h ot M od e
t
Frequ_Detect_Timing_singleShot_wmf
Figure 3-32
Frequency Detection timing in Single Shot mode 67 2002-11-28
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3.7.1
Frequency Window for Data Rate Detection
The high time of data is used to measure the frequency of the data signal. For Manchester coding either the data frequency or half of the data frequency have to be detected corresponding to one high time or twice the high time of data signal. A time period of 3*2*T is necessary to decide about valid or invalid data.
T
2*T
DATA t 0 T2 T1 possible GATE 1 0 2*T2 2*T1 possible GATE 2 0 1 0 1 0
t
t
window_count_timing.wmf
Figure 3-33
Window Counter timing
Example to calculate the thresholds for a given data rate: - Data signal manchester coded - Data Rate: 2kbit//s - fclk= 18,0896 MHz Then the period equals to
1 = 0,5ms 2kbit/s
2xT =
[3 - 36]
respectively the high time is 0,25ms. We set the thresholds to +-10% and get: T1= 0,225ms and T2= 0,275ms The thresholds TH1 and TH2 are calculated with following formulas
f clk 4
TH1 = T1x
[3 - 37]
TH2 = T2 x
f clk 4
68
[3 - 38]
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This yields the following results: TH1~ 1017= 001111111001b TH2~ 1243= 010011011011b which have to be programmed into the D0 to D11 bits of the COUNT_TH1 and COUNT_TH2 registers (subaddresses 06H and 07H), respectively. Default values (window counter inactive): TH1= 000000000000b TH2= 000000000001b Note: The timing window of +-10% of a given high time T in general does not correspond to a frequency window +-10% of the calculated data frequency.
Application
3.7.2
RSSI threshold voltage - RF input power
The RF input power level is corresponding to a certain RSSI voltage, which can be seen in Section 3.5. The threshold TH3 of this RSSI voltage can be calculated with the following formula:
TH3
=
desired
RSSI
threshold 1.2V
voltage
x (2
6
- 1)
[3 - 39]
As an example a desired RSSI threshold voltage of 500mV results in TH3~26=011010b, which has to be written into D0 to D5 of the RSSI_TH3 register (sub address 08H). Default value (RSSI detection inactive): TH3=111111b
3.8
Calculation of ON_TIME and OFF_TIME
[3 - 40] [3 - 41]
ON= (216-1)-(fRC*tON) OFF=( 216-1)-(f
RC*tOFF)
fRC= Frequency of internal RC Oszillator Example: tON= 0,005s, tOFF= 0,055s, fRC= 32300Hz ON= 65535-(32300*0,005) ~ 65373= 1111111101011101b OFF= 65535-(32300*0,055) ~ 63758= 1111100100001110b
The values have to be written into the D0 to D15 bits of the ON_TIME and OFF_TIME registers (subaddresses 04H and 05H).
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Default values: ON= 65215 = 1111111011000000b OFF= 62335 = 1111001110000000b tON ~10ms @ fRC= 32kHz tOFF ~100ms @ fRC= 32kHz
Application
3.9
Example for Self Polling Mode
The settings for Self Polling Mode depend very much on the timing of the transmitted Signal. To create an example we consider following data structure transmitted in FSK.
4 F ra m es
D ata 5 0m s 50m s
D a ta
D ata
D a ta t [m s]
4 00 m s
F ra m edeta ils t [m s] P re am b le D ata
S ync t [m s] S yn cron isation P re am b le
data_timing011.wmf
Figure 3-34
Example for transmitted Data-structure
According to existing synchronization techniques there are some synchronization bursts in front of the data added (code violation!). A minimum of 4 Frames is transmitted. Data are preferably Manchester encoded to get fastest respond out of the Data Rate Detection. Target Application: - received Signal has code violation as described before - total mean current consumption below 1mA - data reception within max. 400ms after first transmitted frame One possible Solution: tON = 15ms, tOFF= 135ms
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This gives 15ms ON time of a total period of 150ms which results in max. 0.9mA mean current consumption in Self Polling Mode. The resulting worst case timing is shown in the following figure:
C a se A : D a ta D a ta D a ta D a ta t [m s] 50m s 15m s 135m s P e n a b le s R e ce ive r u n til D a ta co m p le te d
In te rru p t due Pw dDD
C a se B : D a ta D a ta D a ta D a ta t [m s] 50m s 15m s 135m s P e n a b le s R e ce ive r u n til D a ta co m p le te d
In te rru p t due Pw dDD
C a se C : D a ta D a ta D a ta D a ta t [m s] 50m s 15m s 135m s P e n a b le s R e ce ive r u n til D a ta co m p le te d
In te rru p t due PwdD D
... R e ce ive r e n a b le d
data_timing021.wmf
Figure 3-35 Description:
3 possible timings
Assumption: the ON time comes right after the first frame (Case A). If OFF time is 135ms the receiver turns on during Sync-pulses and the PwdDD- pulse wakes up the P. If the ON time is in the center of the 50ms gap of transmission (Case B), the Data Detect Logic will wake up the P 135ms later. If ON time is over just before Sync-pulses (Case C), next ON time is during Data transmission and Data Detect Logic will trigger a PwdDD- pulse to wake up the P. Note: In this example it is recommended to use the Peak Detector for slicer threshold generation, because of its fast attack and slow release characteristic. To overcome the data zero gap of 50ms larger external capacitors than noted in Section 4.4 at pin12 and 13 are recommended. Further information on calculating these components can be taken from Section 3.6.2.
3.10 3.10.1
Sensitivity Measurements Test Setup
The test setup used for the measurements is shown in the following figure. In case of ASK modulation the Rohde & Schwarz SMIQ generator, which is a vector signal generator, is connected to the I/Q modulation source AMIQ. This "baseband signal generator" is in turn controlled by the PC Preliminary Specification 71 2002-11-28
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based software WinQSIM via a GPIB interface. The AMIQ generator has a pseudo random binary sequence (PRBS) generator and a bit error test set built in. The resulting I/Q signals are applied to the SMIQ to generate a ASK (OOK) spectrum at the desired RF frequency. Data is demodulated by the TDA5255 and then sent back to the AMIQ to be compared with the originally sent data. The bit error rate is calculated by the bit error rate equipment inside the AMIQ. Baseband coding in the form of Manchester is applied to the I signal as can be seen in the subsequent figure.
P e rso n a l C o m p u te r S o ftw a re W inIQ SIM G P IB / R S 232 A M IQ B E R T M a rke r O u tp u t R o h d e & S ch w a rz I/Q M o d u la tio n S o u rce A M IQ I Q (B it E rro r R a te T e st S e t)
C lo ck
D a ta
M a n ch e ste r E n co d e r
M a n ch e ste r D e co d e r
D ATAout R o h d e & S ch w a rz V e cto r S ig n a l G e n e ra to r S M IQ 0 3 A S K / F S K R F S ig n a l R F in DUT T ra n sce ive r T e stb o a rd TD A 525x
TestSetup.wmf
Figure 3-36
BER Test Setup
In the following figures the RF power level shown is the average power level. These investigations have been made on an Infineon evaluation board using a data rate of 4 kBit/ s with manchester encoding and a data filter bandwidth of 7 kHz. This is the standard configuration of our evaluation boards. All these measurements have been performed with several evaluation boards, so that production scattering and component tolerances are already included in these results. Regarding the data filter bandwidth it has to be mentioned that a data rate of 4 kBit/s using manchester encoding results in a data frequency of 2 kHz to 4 kHz depending on the occurring data pattern. The test pattern given by the AMIQ is a pseudo random binary sequency (PRBS9) with a 9 bit shift register. This pattern varies the resulting data frequency up to 4 kHz.
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The best sensitivity performance can be achieved using a data filter bandwidth of 1.25 times the maximum occuring data frequency. The IQ filter setting is depending on the modulation type. ASK needs an IQ filter of 50kHz, 50kHz deviation at FSK recommend a 100kHz IQ filter and 100kHz deviation were measured with a 150kHz IQ filter A very practicable configuration is to set the chip-internal adjustable IQ filter to the sum of FSK peak deviation and maximum datafrequency. Concerning these aspects the bandwidth should be chosen small enough. With respect to both, the crystal tolerances and the tolerances of the crystal oscillator circuit of receiver and transmitter as well, a too small IQ filter bandwidth will reduce the sensitivity again. So a compromise has to be made. For further details on chip tolerances see also Section 3.2.7
3.10.2
BER performance depending on Supply Voltage
Due to the wide supply voltage range of this transeiver chip also the sensitivity behaviour over this parameter is documented is the subsequent graph.
BER_VCC.wmf
Figure 3-37
BER supply voltage
Please notice the tiny sensitivity changes of 1.0 to 1.5dB, when variing the supply voltage.
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3.10.3
Datarates and Sensitivity
The TDA 5255 can handle datarates up to 64kbit/s, as can be taken from the following figure. (see Section 4.1.4)
BER_Datarate.wmf
Figure 3-38
Datarates and Sensitivity
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3.11
Default Setup
Default setup is hard wired on chip and effective after a reset or return of power supply.
Table 3-14
Default Setup Parameter
Value 150kHz 7kHz 470Hz RC 4.5pF 2.5pF 1.5pF HIGH HIGH 2.6ms RSSI 10ms 100ms 1MHz 1MHz bipolar off PWDN Slave
IFX-Board
Comment
IQ-Filter Bandwidth Data Filter Bandwidth Limiter lower fg Slicing Level Generation Nom. Frequency Capacity intern (ASK TX, FSK RX) FSK+ Frequency Capacity intern (FSK+, ASK RX) FSK- Frequency Capacity intern (FSK-) LNA Gain Power Amplifier RSSI accuracy settling time ADC measurement ON-Time OFF-Time Clock out RX PowerON Clock out TX PowerON Clock out RX PowerDOWN Clock out TX PowerDOWN XTAL modulation switch XTAL modulation shaping RX / TX ASK/FSK PwdDD Operating Mode
47nF 10nF 434.16MHz +35kHz -35kHz
+10dBm 2.2nF
Jumper Jumper Jumper removed
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4
4.1 4.1.1
Reference
Electrical Data Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 4-1 # 1 2 3 4 5
Absolute Maximum Ratings Parameter Symbol Supply Voltage Junction Temperature Storage Temperature Thermal Resistance ESD integrity, all pins Vs Tj Ts RthJA VESD
Limit Values min max -0.3 5.8 -40 +125 -40 +150 114 tbd tbd
Unit V C C K/W kV
Remarks
HBM according to MIL STD 883D, method 3015.7
4.1.2
Operating Range
Within the operational range the IC operates as explained in the circuit description. Table 4-2 Operating Range Parameter Symbol # 1 2 3 4 Supply voltage Ambient temperature Receive frequency Transmit frequency
VS
TA fRX fTX
Limit Values min max 2.1 5.5 -40 85 433 435 433 435
Unit Test Conditions L V C MHz MHz
Item
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4.1.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. Table 4-3 AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V # Parameter Symbol Limit Values Unit Test Conditions min typ max RECEIVER Characteristics 1 Supply current RX FSK IRX_FSK 2 Supply current RX FSK IRX_FSK 3 Supply current RX ASK IRX_ASK 4 Supply current RX ASK IRX_ASK 5 Sensitivity FSK 10-3 BER RFsens 9 9.5 8.6 9.1 -109 mA mA mA mA 3V, FSK, Default 5V, FSK, Default 3V, ASK, Default 5V, ASK, Default
L Item
6
Sensitivity ASK 10-3 BER
RFsens
-109
dBm FSK@35kHz, 4kBit/s X Manch. Data, Default 7kHz datafilter, 50kHz IQ filter dBm ASK, 4kBit/s Manch. X data, Default setup 7kHz datafilter, 50kHz IQ filter nA 12 ms 5.5V, all power down
7
Power down current
8 System setup time (1st power on or reset) 9 Clock Out setup time 10 11 12 13 Receiver setup time Data detection setup time RSSI stable time Data Valid time
IPWDN_R X tSYSSU tCLKSU tRXSU tDDSU tRSSI tData_Vali d P1dB P1dB_low VBL_1MH z PLO
5 4 8 0.5 1.54 1.82 1.82 2.2 2.6 2.6 3.35
ms stable CLKDIV output signal 2.86 ms DATA out (valid or invalid) 3.38 ms Begin of Data detection 3.38 ms ms RFin -100dBm see chapter 4.5 4kBit/s Manch. detected (valid) X X X X
14 15 16 17
Input P1dB, high gain Input P1dB, low gain
Selectivity
-48dBm -32dBm 50 -102 78
LO leakage
dBm 3V, Default, high gain dBm 3V, Default, low gain dB fRF+/-1MHz, Default, RFsens+3dB dBm 578,9MHz
Preliminary Specification
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Table 4-3 AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V # Parameter Symbol Limit Values Unit Test Conditions min typ max TRANSMITTER Characteristics 1 Supply current TX, FSK 2 Supply current TX, FSK 3 Supply current TX, FSK 4 5 6 Output power Output power Output power ITX ITX ITX Pout Pout Pout ITX ITX ITX Pout_low Pout_low Pout_low IPWDN_T X tCLKSU tTXSU 0.77 10,7 13,3 17,4 6 9 13 5,2 7,2 13,9 -32 -2,5 10,4 5 mA mA mA dBm dBm dBm mA mA mA dBm dBm dBm nA 2.1V, high power 3V, high power 5V, high power 2.1V, high power 3V, high power 5V, high power 2.1V, low power 3V, low power 5V, low power 2.1V, low power 3V, low power 5V, low power 5.5V, all power down X X X X X X 1 1 1 1 1 1
Reference
L Item
7 Supply current TX, FSK 8 Supply current TX, FSK 9 Supply current TX, FSK 10 11 12 13 Output power Output power Output power Power down current
14 Clock Out setup time 15 Transmitter setup time
0.5 1.1
ms stable CLKDIV output signal 1.43 ms PWDN-->PON or X RX-->TX dBm dBm dBm dBm 3V, 50Ohm Board, Default (1MHz) 3V, 50Ohm Board 3V, 50Ohm Board 3V, 50Ohm Board X X X X
16
Spurious fRF+/-fclock
Pclock P1st P2nd P3rd
-44 -71 -45 -48
17 Spurious fRF+/-fXTAL 18 Spurious 2nd harmonic 19 Spurious 3rd harmonic
1: without pin diode current (RX/TX-switch) 130uA@2.1V; 310uA@3V; 720uA@5V
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Table 4-4 AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V # Parameter Symbol Limit Values Unit Test Conditions min typ max GENERAL Characteristics 1 Power down current timer mode (standby) 2 Power down current timer mode (standby) 3 Power down current with XTAL ON 4 Power down current with XTAL ON 5 6 7 8 32kHz oscillator freq. XTAL startup time IPWDN_32k IPWDN_32k IPWDN_Xtl IPWDN_Xtl 9 11 750 860 uA uA uA uA 3V, 32kHz clock on 5V, 32kHz clock on 3V, CONFIG9=1 5V, CONFIG9=1
L Item
f32kHz tXTAL CC0max RRmax LOSC LOSC
24
32 0.5 5
40
kHz ms IFX Board with Crystal Q1 as X
specified in Section 4.4
Load capacitance Serial resistance of the crystal 9 Input inductance XOUT 10 Input inductance XOUT
100 2.7 2.45
pF W
X X
uH with pad on evaluation board X uH without pad on evaluation X
board
11 FSK demodulator gain
GFSK
2.4
mV/ kHz V V V V mV/ dB default setup default setup default setup default setup default setup X X X X X
12 13 14 15 16
RSSI@-120dBm RSSI@-100dBm RSSI@-70dBm RSSI@-50dBm RSSI Gradient
U-120dBm U-100dBm U-70dBm U-50dBm GRSSI
0.35 0.55 1 1.2 14
17 18 19 20
IQ-Filter bandwidth Data Filter bandwidth Vcc-Vtune RX, Pin3 Vcc-Vtune TX, Pin3
f3dB_IQ f3dB_LP
115 150 185 kHz 5.3 7 8.7 kHz 1 1.1 1.6 1.6 V V
Default setup Default setup fRef=18.08956MHz fRef=18.08956MHz
X X
Vcc-tune,RX 0.5 Vcc-tune,TX 0.5
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4.1.4
Digital Characteristics
I2C Bus Timing
BusMode = LOW
t BUF
BusData
tH D.ST A tF t SP
tR tL OW
BusCLK
t HIG H
tH D.ST A
t HD. DAT
t H IG H
tSU .DAT
t SU. STA
t SU.S TO
EN pulsed or mandatory low
t SU. ENAS DA t SU. ENAS DA
tSU. ENA SDA
Figure 4-1
I2C Bus Timing
3-wire Bus Timing
BUS_MODE = HIGH
SDA
t Wt LO R
tSP tF
SCL
tSU ST .A
tHD.DA T
t I GH H
tSU D . AT
tSU.STO
BUS_ENA
tW E HN
Figure 4-2
3-wire Bus Timing
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Table 4-5 # 1 2
3 4 5
Digital Characteristics with TA = 25 C, VVdd = 2.1 ... 5.5 V Parameter Symbol Limit Values Unit Test Conditions min typ max Data rate TX ASK fTX.ASK 10 100 kBaud PRBS9, Manch.@+9dBm Data rate TX FSK fTX.FSK 10 32 kBaud PRBS9, Manch.@+9dBm @35kHz dev. Data rate RX ASK fRX.ASK 10 50 kBaud PRBS9, Manch. Data rate RX FSK fRX.FSK 10 64 kBaud PRBS9, Manch. @100kHz dev. Data rate RX FSK fRX.FSK 10 28.8 kBaud PRBS9, Manch. @35kHz dev. VIH VIL VOL Vdd0.2 0 0.4 1.15 35 30 Vdd0.4 0.4 Vdd 0.2 V V V V ns ns V V @Vdd=3V Isink=800uA Isink=3mA @Vdd=3V load 10pF load 10pF Isorce=350uA Isink=400uA
L Item X X 1 1
X X X
Digital Inputs High-level Input Voltage Low-level Input Voltage 7 RXTX Pin 5 TX operation, int. controlled 8 CLKDIV Pin 26 trise (0.1*Vdd to 0.9*Vdd) tfall (0.9*Vdd to 0.1*Vdd) Output High Voltage Output Low Voltage
6
X
X
tr tf VOH VOL
X
Bus Interface Characteristics
9 Pulse width of spikes which tSP must be suppressed by the input filter 10 LOW level output voltage at VOL BusData 11 SLC clock frequency fSLC 12 Bus free time between STOP tBUF and START condition 13 Hold time (repeated) START tHO.STA condition.
0
50
ns
Vdd=5V
X
0.4 0 1.3 0.6 400
V kHz s s
3mA sink current Vdd=5V Vdd=5V only I2C mode Vdd=5V After this period, the first clock pulse is generated, only I2C
X X X X
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Table 4-5 #
Reference
Digital Characteristics with TA = 25 C, VVdd = 2.1 ... 5.5 V Parameter Symbol Limit Values Unit Test Conditions min typ max 14 LOW period of BusCLK clock tLOW 1.3 s Vdd=5V 15 HIGH period of BusCLK tHIGH 0.6 s Vdd=5V clock 16 Setup time for a repeated tSU.STA 0.6 s only I2C mode START condition 17 Data hold time tHD.DAT 0 ns Vdd=5V 18 Data setup time tSU.DAT 100 ns Vdd=5V tR, tF 19 Rise, fall time of both 20+ 300 ns Vdd=5V BusData and BusCLK 0.1Cb signals 20 Setup time for STOP tSU.STO 0.6 s only I2C mode condition Vdd=5V 21 Capacitive load for each bus Cb 400 pF Vdd=5V line 22 Setup time for BusCLK to EN tSU.SCLE 0.6 s only 3-wire mode Vdd=5V N 23 H-pulsewidth (EN) tWHEN 0.6 s Vdd=5V
L Item X X X X X X
2
X X X X
1: limited by transmission channel bandwidth and depending on transmit power level; ETSI regulation EN 300 220 fullfilled, see Section 3.1 2: Cb= capacitance of one bus line
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4.2
Test Circuit
The device performance parameters marked with X in Section 4.1.3 were measured on an Infineon evaluation board (IFX board).
TDA5250_v41.schematic.pdf
Figure 4-3
Schematic of the Evaluation Board 84 2002-11-28
Preliminary Specification
TDA5255 E1 Version 1.1
Confidential Reference
4.3
Test Board Layout
Gerberfiles for this Testboard are available on request.
TDA5250_v41_layout.pdf
Figure 4-4
Layout of the Evaluation Board
Note 1: The LNA and PA matching network was designed for minimum required space and maximum performance and thus via holes were deliberately placed into solder pads. In case of reproduction please bear in mind that this may not be suitable for all automatic soldering processes. Note 2: Please keep in mind not to layout the CLKDIV line directly in the neighborhood of the crystal and the associated components.
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Note 3: Difference in supply voltage especially between pin 1 and pin 15 is recommended to be lower than 30mV, therefore a serial resistor in the VDD supply line, as mentioned on page 13 and in Section 4.4, is strongly recommended. The opto part (X4) should be supplied by connecting to X3.
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4.4
Bill of Materials
Table 4-6 Bill of Materials Reference R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13
Value 4k7 0 --1M 4k7 4k7 4k7 6k8 180 180 270 15k 10k 180 180 1M 1M 1M 560 1k 0 0 10 100pF 3,3pF 18pF 8,2pF 1nF 1nF 2,7pF --10pF 100pF --10nF 10nF
Specification 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
Tolerance +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-0,1pF +/-1% +/-0,1pF +/-5% +/-5% +/-0,1pF +/-0,1pF +/-1% +/-5% +/-5% +/-10% +/-10%
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Table 4-6 Bill of Materials Reference Value C14 10nF C15 10pF C16 1.8pF 15pF C17 C18 10nF C19 2,2nF C20 47nF C21 47nF C22 47nF 47nF C23 C24 100nF C25 100nF C26 --C27 100nF C28 100nF 100nF C29 C30 --L1 100nH L2 18nH L3 39nH IC1 TDA5255 E1 IC2 ILQ74 IC3 SFH6186 Q1 18.08958MHz S1 1-pol. T1 BC847B D1, D2 BAR63-02W X1, X2 SMA-socket X5 SubD 25p.
Reference
Specification 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 SIMID 0603-C (EPCOS) SIMID 0603-C (EPCOS) SIMID 0603-C (EPCOS) PTSSOP38
Tolerance +/-10% +/-0,1pF +/-0,1pF +/-1% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-2% +/-2% +/-2%
Telcona: C0=2,1pF SOT-23 (Infineon) SCD-80 (Infineon)
C1=8fF, CL=20pF
Note: Serial resistors in supply lines (R21, R22, R23) should be equipped as shown in the table above.
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List of Tables
Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 2-17 Table 2-18 Table 2-19 Table 2-20 Table 2-21 Table 2-22 Table 2-23 Table 2-24 Table 2-25 Table 2-26 Table 2-27 Table 2-28 Table 2-29 Table 2-30 Table 2-31 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PwdDD Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip address Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Write Mode 8 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Write Mode 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-wire Bus Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-wire Bus Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Addresses of Data Registers Write. . . . . . . . . . . . . . . . . . . . . . Sub Addresses of Data Registers Read. . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 01H: FSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 02H: XTAL_TUNING . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 03H: LPF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Addresses 04H / 05H: ON/OFF_TIME . . . . . . . . . . . . . . . . . . . Sub Address 06H: COUNT_TH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 07H: COUNT_TH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 08H: RSSI_TH3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 0DH: CLK_DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 0EH: XTAL_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 0FH: BLOCK_PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 80H: STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 81H: ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE settings: CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV Output Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Source for 6Bit-ADC Selection (Register 08H). . . . . . . . . . . . . . . . . Crystal and crystal oscilator dependency . . . . . . . . . . . . . . . . . . . . . Typical values of parasitic capacitances . . . . . . . . . . . . . . . . . . . . . . Sub Address 0EH: XTAL_CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 02H: XTAL_TUNING . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 01H: FSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default oscillator settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Setup (without internal tuning & without Pin21 usage) . . . . . 3dB cutoff frequencies I/Q Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3dB cutoff frequencies Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . Limiter Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 11 page 18 page 18 page 21 page 22 page 23 page 25 page 25 page 25 page 25 page 26 page 26 page 27 page 27 page 27 page 28 page 28 page 28 page 28 page 28 page 28 page 29 page 29 page 29 page 29 page 29 page 29 page 30 page 35 page 35 page 35 page 49 page 54 page 56 page 56 page 56 page 57 page 57 page 57 page 58 page 60 page 61 page 62
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List of Tables
Table 3-13 Table 3-14 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V . . . . . AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V . . . . . Digital Characteristics with TA = 25 C, VVdd = 2.1 ... 5.5 V . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 63 page 75 page 77 page 77 page 78 page 80 page 82 page 86
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List of Figures
Figure 1-1 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Figure 2-13 Figure 2-14 Figure 2-15 Figure 2-16 Figure 2-17 Figure 2-18 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-21 Figure 3-22 Figure 3-23 Figure 3-24 P-TSSOP-38-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . page Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page One I/Q Filter stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Quadricorrelator Demodulation Characteristic . . . . . . . . . . . . . . . . . page Data Filter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Sub Addresses Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Wakeup Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Timing for Self Polling Mode (ADC & Data Detect in one shot mode) page Timing for Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Frequency and RSSI Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Data Valid Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Data Input/Output Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 1st start or reset in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 1st start or reset in PD mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Sequencer`s capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page S11 measured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page TX_Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page TX_Mode_simplified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Equivalent power amplifier tank circuit . . . . . . . . . . . . . . . . . . . . . . . page Output power Po (mW) and collector efficiency E vs. load resistor RL. page Power output and collector current vs. frequency . . . . . . . . . . . . . . . page Sparam_measured_200M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Transmit Spectrum 3GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Transmit Spectrum 300MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page ASK Transmit Spectrum 100kBaud, Manch, PRBS9, 9dBm, 3V . . . page FSK Transmit Spectrum 32kBaud, Manch, PRBS9, 9dBm, 3V . . . . page Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page possible crystal oscillator frequencies . . . . . . . . . . . . . . . . . . . . . . . . page FSK modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page FSK receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page parasitics of the switching network . . . . . . . . . . . . . . . . . . . . . . . . . . page I/Q Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page IQ Filter and frequency characteristics of the receive system. . . . . . page Limiter and Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Limiter frequency characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . page Typ. RSSI Level (Eval Board) @3V . . . . . . . . . . . . . . . . . . . . . . . . . page 90 9 10 17 19 20 21 22 23 26 30 30 31 31 32 32 33 33 34 34 37 38 39 41 41 42 43 44 45 46 46 47 47 48 50 51 52 53 54 59 59 60 61 62
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Confidential
List of Figures
Figure 3-25 Figure 3-26 Figure 3-27 Figure 3-28 Figure 3-29 Figure 3-30 Figure 3-31 Figure 3-32 Figure 3-33 Figure 3-34 Figure 3-35 Figure 3-36 Figure 3-37 Figure 3-38 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Slicer Level using RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slicer Level using Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detector timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detector as analog Buffer (v=1) . . . . . . . . . . . . . . . . . . . . . . . . Peak detector - power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . Power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Detection timing in continuous mode . . . . . . . . . . . . . . . Frequency Detection timing in Single Shot mode . . . . . . . . . . . . . . . Window Counter timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for transmitted Data-structure. . . . . . . . . . . . . . . . . . . . . . . 3 possible timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BER Test Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BER supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Datarates and Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . Layout of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page page page page page page page page page page page page page page page page page page 63 64 64 65 66 66 67 67 68 70 71 72 73 74 81 81 84 85
Preliminary Specification
91
2002-11-28
TDA5255 E1 Version 1.1
Confidential
Index
A Absolute Maximum Ratings 77 AC/DC Characteristics 78 Application 9, 37 E Electrical Data 77 F Features 8 Functional Block Description 18 Functional Block Diagram 17 Functional Description 10 O Operating Range 77 Overview 8 P Package Outlines 9 Pin Configuration 10 Pin Definitions and Functions 11 Product Description 8 R Reference 77 S Standards 81
Preliminary Specification
92
2002-11-28

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